30 #define QQQdialect MPLABX 44 #undef QQQMULTIPROCESSEXH 47 #define qqqMaxBranchDepth 20 48 #define QQQstructbitmap 60 #undef QQQTEMPLATEONLY 62 #define QQQUPLOADATEND 64 #undef QQQASHLINGVITRA 66 #define qqqbitmapint unsigned int 68 #undef QQQTIC2XSERIALIO 70 #undef QQQCOMPRESSED_EXH 77 #define wl_sps_50zzopen zzopen 79 #define wl_sps_50zqqzqz1 zqqzqz1 82 #define FILEPOINT FILE * f, 83 #if !defined(QQQTEMPLATEONLY) && !defined(FILE) && !defined(QQQNOSTDIO) 99 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port.h" 100 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port_common.h" 103 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port.c" 104 #include "C:\LDRA_Toolsuite\Compiler_spec\Microchip\Mplabx_xc32_script\ldra_port_common.c" 112 #if defined(QQQstructbitmap) && defined(QQQSINGLEFILE) 113 #ifndef LDRA_VOID_FUNC 114 #define LDRA_VOID_FUNC 117 #if defined(QQQMAINFL) 140 #ifdef QQQ_KEEPCOMMENTS 148 #if !defined(QQQSUPPRESS_UNDEF) 154 #undef QQQHITMAP_STORAGE 156 #define qqnull_params void 157 #define QQQ_PROTOTYPE_DEF 159 #undef QQ_ANSI_PROTOTYPE 161 #define QQ_ANSI_PROTOTYPE 1 164 #define QQ_ANSI_PROTOTYPE 1 170 #define ELEMENT(N) qqqbitmapint element##N; 172 #include "wl_sps_50zbelem.def" 176 #define ELEMENT(N) 0, 178 #include "wl_sps_50zbelem.def" 257 #ifndef _SYSTEM_CONFIG_H 258 #define _SYSTEM_CONFIG_H 277 #define SYS_VERSION_STR "2.06" 278 #define SYS_VERSION 20600 282 #define SYS_CLK_FREQ 200000000ul 283 #define SYS_CLK_BUS_PERIPHERAL_1 100000000ul 284 #define SYS_CLK_BUS_PERIPHERAL_2 100000000ul 285 #define SYS_CLK_BUS_PERIPHERAL_3 100000000ul 286 #define SYS_CLK_BUS_PERIPHERAL_4 100000000ul 287 #define SYS_CLK_BUS_PERIPHERAL_5 100000000ul 288 #define SYS_CLK_BUS_PERIPHERAL_7 200000000ul 289 #define SYS_CLK_BUS_PERIPHERAL_8 100000000ul 290 #define SYS_CLK_CONFIG_PRIMARY_XTAL 0ul 291 #define SYS_CLK_CONFIG_SECONDARY_XTAL 32768ul 293 #define SYS_PORT_A_ANSEL 0x3F00 294 #define SYS_PORT_A_TRIS 0xFFED 295 #define SYS_PORT_A_LAT 0x0010 296 #define SYS_PORT_A_ODC 0x0000 297 #define SYS_PORT_A_CNPU 0x0020 298 #define SYS_PORT_A_CNPD 0x0000 299 #define SYS_PORT_A_CNEN 0x0021 300 #define SYS_PORT_B_ANSEL 0x10C8 301 #define SYS_PORT_B_TRIS 0x91FF 302 #define SYS_PORT_B_LAT 0x0000 303 #define SYS_PORT_B_ODC 0x0000 304 #define SYS_PORT_B_CNPU 0x0000 305 #define SYS_PORT_B_CNPD 0x0000 306 #define SYS_PORT_B_CNEN 0x0000 307 #define SYS_PORT_C_ANSEL 0xCFE1 308 #define SYS_PORT_C_TRIS 0xFFFF 309 #define SYS_PORT_C_LAT 0x0000 310 #define SYS_PORT_C_ODC 0x0000 311 #define SYS_PORT_C_CNPU 0x0000 312 #define SYS_PORT_C_CNPD 0x0000 313 #define SYS_PORT_C_CNEN 0x0000 314 #define SYS_PORT_D_ANSEL 0xC100 315 #define SYS_PORT_D_TRIS 0xFFFF 316 #define SYS_PORT_D_LAT 0x0000 317 #define SYS_PORT_D_ODC 0x0000 318 #define SYS_PORT_D_CNPU 0x0000 319 #define SYS_PORT_D_CNPD 0x0000 320 #define SYS_PORT_D_CNEN 0x0000 321 #define SYS_PORT_E_ANSEL 0xFC00 322 #define SYS_PORT_E_TRIS 0xFDFF 323 #define SYS_PORT_E_LAT 0x0000 324 #define SYS_PORT_E_ODC 0x0000 325 #define SYS_PORT_E_CNPU 0x0000 326 #define SYS_PORT_E_CNPD 0x0000 327 #define SYS_PORT_E_CNEN 0x0000 328 #define SYS_PORT_F_ANSEL 0xCEC0 329 #define SYS_PORT_F_TRIS 0xEFFF 330 #define SYS_PORT_F_LAT 0x0000 331 #define SYS_PORT_F_ODC 0x0000 332 #define SYS_PORT_F_CNPU 0x0000 333 #define SYS_PORT_F_CNPD 0x0000 334 #define SYS_PORT_F_CNEN 0x0000 335 #define SYS_PORT_G_ANSEL 0x8CBC 336 #define SYS_PORT_G_TRIS 0xDFFF 337 #define SYS_PORT_G_LAT 0x0000 338 #define SYS_PORT_G_ODC 0x0000 339 #define SYS_PORT_G_CNPU 0x0000 340 #define SYS_PORT_G_CNPD 0x0000 341 #define SYS_PORT_G_CNEN 0x0000 342 #define SYS_PORT_H_ANSEL 0x0070 343 #define SYS_PORT_H_TRIS 0xB3FB 344 #define SYS_PORT_H_LAT 0x0000 345 #define SYS_PORT_H_ODC 0x0000 346 #define SYS_PORT_H_CNPU 0x0000 347 #define SYS_PORT_H_CNPD 0x0000 348 #define SYS_PORT_H_CNEN 0x0000 349 #define SYS_PORT_J_ANSEL 0x0000 350 #define SYS_PORT_J_TRIS 0x8B7F 351 #define SYS_PORT_J_LAT 0x0080 352 #define SYS_PORT_J_ODC 0x0000 353 #define SYS_PORT_J_CNPU 0x0000 354 #define SYS_PORT_J_CNPD 0x0000 355 #define SYS_PORT_J_CNEN 0x0800 356 #define SYS_PORT_K_ANSEL 0xFF00 357 #define SYS_PORT_K_TRIS 0xFFFF 358 #define SYS_PORT_K_LAT 0x0000 359 #define SYS_PORT_K_ODC 0x0000 360 #define SYS_PORT_K_CNPU 0x0000 361 #define SYS_PORT_K_CNPD 0x0000 362 #define SYS_PORT_K_CNEN 0x0000 366 #define SYS_TMR_POWER_STATE SYS_MODULE_POWER_RUN_FULL 367 #define SYS_TMR_DRIVER_INDEX DRV_TMR_INDEX_0 368 #define SYS_TMR_MAX_CLIENT_OBJECTS 5 369 #define SYS_TMR_FREQUENCY 1000 370 #define SYS_TMR_FREQUENCY_TOLERANCE 10 371 #define SYS_TMR_UNIT_RESOLUTION 10000 372 #define SYS_TMR_CLIENT_TOLERANCE 10 373 #define SYS_TMR_INTERRUPT_NOTIFICATION false 379 #define DRV_IC_DRIVER_MODE_STATIC 382 #define DRV_SPI_NUMBER_OF_MODULES 6 385 #define DRV_SPI_POLLED 1 386 #define DRV_SPI_ISR 0 387 #define DRV_SPI_MASTER 1 388 #define DRV_SPI_SLAVE 0 390 #define DRV_SPI_EBM 1 391 #define DRV_SPI_8BIT 1 392 #define DRV_SPI_16BIT 1 393 #define DRV_SPI_32BIT 0 394 #define DRV_SPI_DMA 0 396 #define DRV_SPI_INSTANCES_NUMBER 3 397 #define DRV_SPI_CLIENTS_NUMBER 3 398 #define DRV_SPI_ELEMENTS_PER_QUEUE 10 400 #define DRV_SPI_SPI_ID_IDX0 SPI_ID_1 401 #define DRV_SPI_TASK_MODE_IDX0 DRV_SPI_TASK_MODE_POLLED 402 #define DRV_SPI_SPI_MODE_IDX0 DRV_SPI_MODE_MASTER 403 #define DRV_SPI_ALLOW_IDLE_RUN_IDX0 false 404 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX0 DRV_SPI_PROTOCOL_TYPE_FRAMED 405 #define DRV_SPI_FRAME_SYNC_PULSE_IDX0 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 406 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX0 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 407 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX0 SPI_FRAME_PULSE_DIRECTION_OUTPUT 408 #define DRV_SPI_FRAME_PULSE_EDGE_IDX0 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 409 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX0 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 410 #define DRV_SPI_COMM_WIDTH_IDX0 SPI_COMMUNICATION_WIDTH_16BITS 411 #define DRV_SPI_CLOCK_SOURCE_IDX0 SPI_BAUD_RATE_PBCLK_CLOCK 412 #define DRV_SPI_SPI_CLOCK_IDX0 CLK_BUS_PERIPHERAL_2 413 #define DRV_SPI_BAUD_RATE_IDX0 1000000 414 #define DRV_SPI_BUFFER_TYPE_IDX0 DRV_SPI_BUFFER_TYPE_ENHANCED 415 #define DRV_SPI_CLOCK_MODE_IDX0 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 416 #define DRV_SPI_INPUT_PHASE_IDX0 SPI_INPUT_SAMPLING_PHASE_IN_MIDDLE 417 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX0 0xFFFF 418 #define DRV_SPI_QUEUE_SIZE_IDX0 10 419 #define DRV_SPI_RESERVED_JOB_IDX0 1 421 #define DRV_SPI_SPI_ID_IDX1 SPI_ID_2 422 #define DRV_SPI_TASK_MODE_IDX1 DRV_SPI_TASK_MODE_POLLED 423 #define DRV_SPI_SPI_MODE_IDX1 DRV_SPI_MODE_MASTER 424 #define DRV_SPI_ALLOW_IDLE_RUN_IDX1 false 425 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX1 DRV_SPI_PROTOCOL_TYPE_FRAMED 426 #define DRV_SPI_FRAME_SYNC_PULSE_IDX1 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 427 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX1 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 428 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX1 SPI_FRAME_PULSE_DIRECTION_OUTPUT 429 #define DRV_SPI_FRAME_PULSE_EDGE_IDX1 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 430 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX1 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 431 #define DRV_SPI_COMM_WIDTH_IDX1 SPI_COMMUNICATION_WIDTH_8BITS 432 #define DRV_SPI_CLOCK_SOURCE_IDX1 SPI_BAUD_RATE_PBCLK_CLOCK 433 #define DRV_SPI_SPI_CLOCK_IDX1 CLK_BUS_PERIPHERAL_2 434 #define DRV_SPI_BAUD_RATE_IDX1 1000000 435 #define DRV_SPI_BUFFER_TYPE_IDX1 DRV_SPI_BUFFER_TYPE_ENHANCED 436 #define DRV_SPI_CLOCK_MODE_IDX1 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 437 #define DRV_SPI_INPUT_PHASE_IDX1 SPI_INPUT_SAMPLING_PHASE_IN_MIDDLE 438 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX1 0xFF 439 #define DRV_SPI_QUEUE_SIZE_IDX1 10 440 #define DRV_SPI_RESERVED_JOB_IDX1 1 442 #define DRV_SPI_SPI_ID_IDX2 SPI_ID_4 443 #define DRV_SPI_TASK_MODE_IDX2 DRV_SPI_TASK_MODE_POLLED 444 #define DRV_SPI_SPI_MODE_IDX2 DRV_SPI_MODE_MASTER 445 #define DRV_SPI_ALLOW_IDLE_RUN_IDX2 false 446 #define DRV_SPI_SPI_PROTOCOL_TYPE_IDX2 DRV_SPI_PROTOCOL_TYPE_FRAMED 447 #define DRV_SPI_FRAME_SYNC_PULSE_IDX2 SPI_FRAME_SYNC_PULSE_ON_EVERY_DATA_CHARACTER 448 #define DRV_SPI_FRAME_PULSE_POLARITY_IDX2 SPI_FRAME_PULSE_POLARITY_ACTIVE_LOW 449 #define DRV_SPI_FRAME_PULSE_DIRECTION_IDX2 SPI_FRAME_PULSE_DIRECTION_OUTPUT 450 #define DRV_SPI_FRAME_PULSE_EDGE_IDX2 SPI_FRAME_PULSE_EDGE_COINCIDES_FIRST_BIT_CLOCK 451 #define DRV_SPI_FRAME_PULSE_WIDTH_IDX2 SPI_FRAME_PULSE_WIDTH_ONE_WORD_LENGTH 452 #define DRV_SPI_COMM_WIDTH_IDX2 SPI_COMMUNICATION_WIDTH_16BITS 453 #define DRV_SPI_CLOCK_SOURCE_IDX2 SPI_BAUD_RATE_PBCLK_CLOCK 454 #define DRV_SPI_SPI_CLOCK_IDX2 CLK_BUS_PERIPHERAL_2 455 #define DRV_SPI_BAUD_RATE_IDX2 500000 456 #define DRV_SPI_BUFFER_TYPE_IDX2 DRV_SPI_BUFFER_TYPE_ENHANCED 457 #define DRV_SPI_CLOCK_MODE_IDX2 DRV_SPI_CLOCK_MODE_IDLE_LOW_EDGE_FALL 458 #define DRV_SPI_INPUT_PHASE_IDX2 SPI_INPUT_SAMPLING_PHASE_AT_END 459 #define DRV_SPI_TRANSMIT_DUMMY_BYTE_VALUE_IDX2 0x0000 460 #define DRV_SPI_QUEUE_SIZE_IDX2 10 461 #define DRV_SPI_RESERVED_JOB_IDX2 1 463 #define DRV_TMR_INTERRUPT_MODE true 465 #define DRV_TMR_PERIPHERAL_ID_IDX0 TMR_ID_2 466 #define DRV_TMR_INTERRUPT_SOURCE_IDX0 INT_SOURCE_TIMER_2 467 #define DRV_TMR_INTERRUPT_VECTOR_IDX0 INT_VECTOR_T2 468 #define DRV_TMR_ISR_VECTOR_IDX0 _TIMER_2_VECTOR 469 #define DRV_TMR_INTERRUPT_PRIORITY_IDX0 INT_PRIORITY_LEVEL4 470 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX0 INT_SUBPRIORITY_LEVEL0 471 #define DRV_TMR_CLOCK_SOURCE_IDX0 DRV_TMR_CLKSOURCE_INTERNAL 472 #define DRV_TMR_PRESCALE_IDX0 TMR_PRESCALE_VALUE_8 473 #define DRV_TMR_OPERATION_MODE_IDX0 DRV_TMR_OPERATION_MODE_16_BIT 474 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX0 false 475 #define DRV_TMR_POWER_STATE_IDX0 476 #define DRV_TMR_PERIPHERAL_ID_IDX1 TMR_ID_7 477 #define DRV_TMR_INTERRUPT_SOURCE_IDX1 INT_SOURCE_TIMER_7 478 #define DRV_TMR_INTERRUPT_VECTOR_IDX1 INT_VECTOR_T7 479 #define DRV_TMR_ISR_VECTOR_IDX1 _TIMER_7_VECTOR 480 #define DRV_TMR_INTERRUPT_PRIORITY_IDX1 INT_PRIORITY_LEVEL3 481 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX1 INT_SUBPRIORITY_LEVEL0 482 #define DRV_TMR_CLOCK_SOURCE_IDX1 DRV_TMR_CLKSOURCE_INTERNAL 483 #define DRV_TMR_PRESCALE_IDX1 TMR_PRESCALE_VALUE_16 484 #define DRV_TMR_OPERATION_MODE_IDX1 DRV_TMR_OPERATION_MODE_16_BIT 485 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX1 false 486 #define DRV_TMR_POWER_STATE_IDX1 488 #define DRV_TMR_PERIPHERAL_ID_IDX2 TMR_ID_6 489 #define DRV_TMR_INTERRUPT_SOURCE_IDX2 INT_SOURCE_TIMER_6 490 #define DRV_TMR_INTERRUPT_VECTOR_IDX2 INT_VECTOR_T6 491 #define DRV_TMR_ISR_VECTOR_IDX2 _TIMER_6_VECTOR 492 #define DRV_TMR_INTERRUPT_PRIORITY_IDX2 INT_PRIORITY_LEVEL1 493 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX2 INT_SUBPRIORITY_LEVEL0 494 #define DRV_TMR_CLOCK_SOURCE_IDX2 DRV_TMR_CLKSOURCE_INTERNAL 495 #define DRV_TMR_PRESCALE_IDX2 TMR_PRESCALE_VALUE_16 496 #define DRV_TMR_OPERATION_MODE_IDX2 DRV_TMR_OPERATION_MODE_16_BIT 497 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX2 false 498 #define DRV_TMR_POWER_STATE_IDX2 500 #define DRV_TMR_PERIPHERAL_ID_IDX3 TMR_ID_1 501 #define DRV_TMR_INTERRUPT_SOURCE_IDX3 INT_SOURCE_TIMER_1 502 #define DRV_TMR_INTERRUPT_VECTOR_IDX3 INT_VECTOR_T1 503 #define DRV_TMR_ISR_VECTOR_IDX3 _TIMER_1_VECTOR 504 #define DRV_TMR_INTERRUPT_PRIORITY_IDX3 INT_PRIORITY_LEVEL2 505 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX3 INT_SUBPRIORITY_LEVEL0 506 #define DRV_TMR_CLOCK_SOURCE_IDX3 DRV_TMR_CLKSOURCE_INTERNAL 507 #define DRV_TMR_PRESCALE_IDX3 TMR_PRESCALE_VALUE_256 508 #define DRV_TMR_OPERATION_MODE_IDX3 DRV_TMR_OPERATION_MODE_16_BIT 509 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX3 false 510 #define DRV_TMR_POWER_STATE_IDX3 512 #define DRV_TMR_PERIPHERAL_ID_IDX4 TMR_ID_3 513 #define DRV_TMR_INTERRUPT_SOURCE_IDX4 INT_SOURCE_TIMER_3 514 #define DRV_TMR_INTERRUPT_VECTOR_IDX4 INT_VECTOR_T3 515 #define DRV_TMR_ISR_VECTOR_IDX4 _TIMER_3_VECTOR 516 #define DRV_TMR_INTERRUPT_PRIORITY_IDX4 INT_PRIORITY_LEVEL1 517 #define DRV_TMR_INTERRUPT_SUB_PRIORITY_IDX4 INT_SUBPRIORITY_LEVEL0 518 #define DRV_TMR_CLOCK_SOURCE_IDX4 DRV_TMR_CLKSOURCE_INTERNAL 519 #define DRV_TMR_PRESCALE_IDX4 TMR_PRESCALE_VALUE_16 520 #define DRV_TMR_OPERATION_MODE_IDX4 DRV_TMR_OPERATION_MODE_16_BIT 521 #define DRV_TMR_ASYNC_WRITE_ENABLE_IDX4 false 522 #define DRV_TMR_POWER_STATE_IDX4 526 #define DRV_USART_INSTANCES_NUMBER 1 527 #define DRV_USART_CLIENTS_NUMBER 1 528 #define DRV_USART_INTERRUPT_MODE false 529 #define DRV_USART_BYTE_MODEL_SUPPORT true 530 #define DRV_USART_READ_WRITE_MODEL_SUPPORT false 531 #define DRV_USART_BUFFER_QUEUE_SUPPORT false 539 #define DRV_USBHS_DEVICE_SUPPORT true 541 #define DRV_USBHS_HOST_SUPPORT false 543 #define DRV_USBHS_INSTANCES_NUMBER 1 545 #define DRV_USBHS_INTERRUPT_MODE true 547 #define DRV_USBHS_ENDPOINTS_NUMBER 2 550 #define USB_DEVICE_DRIVER_INITIALIZE_EXPLICIT 552 #define USB_DEVICE_INSTANCES_NUMBER 1 554 #define USB_DEVICE_EP0_BUFFER_SIZE 64 556 #define USB_DEVICE_ENDPOINT_QUEUE_DEPTH_COMBINED 2 564 #define LED1Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 565 #define LED1On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 566 #define LED1Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 567 #define LED1StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 ) 568 #define LED1StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_12 , Value ) 570 #define LED2Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 571 #define LED2On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 572 #define LED2Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 573 #define LED2StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 ) 574 #define LED2StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_10 , Value ) 576 #define DMP_FIRE_LEDToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 577 #define DMP_FIRE_LEDOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 578 #define DMP_FIRE_LEDOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 579 #define DMP_FIRE_LEDStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 ) 580 #define DMP_FIRE_LEDStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_9 , Value ) 582 #define HVPS_ENBToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 583 #define HVPS_ENBOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 584 #define HVPS_ENBOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 585 #define HVPS_ENBStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 ) 586 #define HVPS_ENBStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_13 , Value ) 588 #define RLY_HVPS_OUTToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 589 #define RLY_HVPS_OUTOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 590 #define RLY_HVPS_OUTOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 591 #define RLY_HVPS_OUTStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 ) 592 #define RLY_HVPS_OUTStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_14 , Value ) 594 #define RLY_WL_SPS_POLToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 595 #define RLY_WL_SPS_POLOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 596 #define RLY_WL_SPS_POLOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 597 #define RLY_WL_SPS_POLStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 ) 598 #define RLY_WL_SPS_POLStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_2 , Value ) 600 #define RLY_LOGToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 601 #define RLY_LOGOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 602 #define RLY_LOGOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 603 #define RLY_LOGStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 ) 604 #define RLY_LOGStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_9 , Value ) 606 #define RLY_DMP_FIREToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 607 #define RLY_DMP_FIREOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 608 #define RLY_DMP_FIREOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 609 #define RLY_DMP_FIREStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 ) 610 #define RLY_DMP_FIREStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_10 , Value ) 612 #define RLY_AUXToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 613 #define RLY_AUXOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 614 #define RLY_AUXOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 615 #define RLY_AUXStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 ) 616 #define RLY_AUXStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_11 , Value ) 618 #define RLY_CCLToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 619 #define RLY_CCLOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 620 #define RLY_CCLOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 621 #define RLY_CCLStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 ) 622 #define RLY_CCLStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_1 , Value ) 624 #define RLY_WL_MONToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 625 #define RLY_WL_MONOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 626 #define RLY_WL_MONOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 627 #define RLY_WL_MONStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 ) 628 #define RLY_WL_MONStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_12 , Value ) 630 #define RLY_ARMCFToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 631 #define RLY_ARMCFOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 632 #define RLY_ARMCFOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 633 #define RLY_ARMCFStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 ) 634 #define RLY_ARMCFStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_13 , Value ) 636 #define RLY_ARMToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 637 #define RLY_ARMOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 638 #define RLY_ARMOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 639 #define RLY_ARMStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 ) 640 #define RLY_ARMStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_14 , Value ) 642 #define TPAN1Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 643 #define TPAN1On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 644 #define TPAN1Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 645 #define TPAN1StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 ) 646 #define TPAN1StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_10 , Value ) 648 #define TPAN2Toggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 649 #define TPAN2On( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 650 #define TPAN2Off( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 651 #define TPAN2StateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 ) 652 #define TPAN2StateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_11 , Value ) 654 #define FSK_DAC_CSToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 655 #define FSK_DAC_CSOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 656 #define FSK_DAC_CSOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 657 #define FSK_DAC_CSStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 ) 658 #define FSK_DAC_CSStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_4 , Value ) 660 #define RLY_COMMToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 661 #define RLY_COMMOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 662 #define RLY_COMMOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 663 #define RLY_COMMStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 ) 664 #define RLY_COMMStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_14 , Value ) 666 #define FSK_DAC_CLRToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 667 #define FSK_DAC_CLROn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 668 #define FSK_DAC_CLROff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 669 #define FSK_DAC_CLRStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 ) 670 #define FSK_DAC_CLRStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_7 , Value ) 672 #define WL_CPS_SWToggle( ) PLIB_PORTS_PinToggle ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 673 #define WL_CPS_SWOn( ) PLIB_PORTS_PinSet ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 674 #define WL_CPS_SWOff( ) PLIB_PORTS_PinClear ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 675 #define WL_CPS_SWStateGet( ) PLIB_PORTS_PinGetLatched ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 ) 676 #define WL_CPS_SWStateSet( Value ) PLIB_PORTS_PinWrite ( PORTS_ID_0 , PORT_CHANNEL_G , PORTS_BIT_POS_13 , Value ) 678 #define HVPS_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_5 ) 680 #define MAN_SIGStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_A , PORTS_BIT_POS_0 ) 682 #define DMP_FIRE_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_E , PORTS_BIT_POS_8 ) 684 #define NEG_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_4 ) 686 #define POS_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_J , PORTS_BIT_POS_15 ) 688 #define DRUM1_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_2 ) 690 #define SAFE_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_1 ) 692 #define DRUM2_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_0 ) 694 #define LOG_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_3 ) 696 #define AUX_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_B , PORTS_BIT_POS_8 ) 698 #define ARMCF_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_K , PORTS_BIT_POS_1 ) 700 #define ARM_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_K , PORTS_BIT_POS_2 ) 702 #define ARMCF_AUTO_SWStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_13 ) 704 #define FIRE_SW_OFFStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_F , PORTS_BIT_POS_8 ) 706 #define FIRE_SW_ONStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_8 ) 708 #define WL_SPS_POS_DETStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_12 ) 710 #define WL_SPS_NEG_DETStateGet( ) PLIB_PORTS_PinGet ( PORTS_ID_0 , PORT_CHANNEL_H , PORTS_BIT_POS_13 ) 711 #define MAN_CN_PORT_CHANNEL PORT_CHANNEL_A 712 #define MAN_CN_PORT_BIT PORTS_BIT_POS_0 713 #define MAN_CN_PORT_INTERRUPT INT_SOURCE_CHANGE_NOTICE_A 714 #define HVPS_CN_PORT_CHANNEL PORT_CHANNEL_J 715 #define HVPS_CN_PORT_BIT PORTS_BIT_POS_11 716 #define HVPS_CN_PORT_INTERRUPT INT_SOURCE_CHANGE_NOTICE_J 759 #ifndef _SYS_DEFINITIONS_H 760 #define _SYS_DEFINITIONS_H 769 #include "system/common/sys_common.h" 770 #include "system/common/sys_module.h" 815 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 854 #ifndef _DRV_COMMON_H 855 #define _DRV_COMMON_H 957 #define DRV_IO_ISBLOCKING( intent ) ( intent & DRV_IO_INTENT_BLOCKING ) 967 #define DRV_IO_ISNONBLOCKING( intent ) ( intent & DRV_IO_INTENT_NONBLOCKING ) 977 #define DRV_IO_ISEXCLUSIVE( intent ) ( intent & DRV_IO_INTENT_EXCLUSIVE ) 1033 #define DRV_HANDLE_INVALID ( ( ( DRV_HANDLE ) - 1 ) ) 1044 #define DRV_CONFIG_NOT_SUPPORTED ( ( ( unsigned short ) - 1 ) ) 1059 #define _PLIB_UNSUPPORTED 1067 #include "system/common/sys_module.h" 1079 #define DRV_IC_INDEX_0 0 1080 #define DRV_IC_INDEX_1 1 1081 #define DRV_IC_INDEX_2 2 1082 #define DRV_IC_INDEX_3 3 1083 #define DRV_IC_INDEX_4 4 1084 #define DRV_IC_INDEX_5 5 1085 #define DRV_IC_INDEX_6 6 1086 #define DRV_IC_INDEX_7 7 1087 #define DRV_IC_INDEX_8 8 1088 #define DRV_IC_INDEX_9 9 1089 #define DRV_IC_INDEX_10 10 1090 #define DRV_IC_INDEX_11 11 1091 #define DRV_IC_INDEX_12 12 1092 #define DRV_IC_INDEX_13 13 1093 #define DRV_IC_INDEX_14 14 1094 #define DRV_IC_INDEX_15 15 1126 const SYS_MODULE_INDEX index ,
1127 const SYS_MODULE_INIT *
const init ) ;
1149 const SYS_MODULE_INDEX drvIndex ,
1194 const SYS_MODULE_INDEX drvIndex ,
1327 #ifndef _DRV_IC_STATIC_H 1328 #define _DRV_IC_STATIC_H 1329 #define DRV_IC_Open( drvIndex , intent ) ( drvIndex ) 1330 #define DRV_IC_Close( handle ) 1369 #include "system/devcon/sys_devcon.h" 1370 #include "system/clk/sys_clk.h" 1371 #include "system/int/sys_int.h" 1372 #include "system/tmr/sys_tmr.h" 1414 #ifndef _DRV_ADC_STATIC_H 1415 #define _DRV_ADC_STATIC_H 1416 #include <stdbool.h> 1417 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 1418 #include "peripheral/adchs/plib_adchs.h" 1419 #include "peripheral/int/plib_int.h" 1459 uint8_t bufIndex ) ;
1463 uint8_t bufIndex ) ;
1513 #ifndef _DRV_TMR_STATIC_H 1514 #define _DRV_TMR_STATIC_H 1563 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 1564 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 1565 #include "peripheral/tmr/plib_tmr.h" 1601 #ifndef _TMR_DEFINITIONS_PIC32M_H 1602 #define _TMR_DEFINITIONS_PIC32M_H 1660 #include "system/int/sys_int.h" 1661 #include "system/clk/sys_clk.h" 1680 #define DRV_TMR_INDEX_0 0 1681 #define DRV_TMR_INDEX_1 1 1682 #define DRV_TMR_INDEX_2 2 1683 #define DRV_TMR_INDEX_3 3 1684 #define DRV_TMR_INDEX_4 4 1685 #define DRV_TMR_INDEX_5 5 1686 #define DRV_TMR_INDEX_6 6 1687 #define DRV_TMR_INDEX_7 7 1688 #define DRV_TMR_INDEX_8 8 1689 #define DRV_TMR_INDEX_9 9 1690 #define DRV_TMR_INDEX_10 10 1691 #define DRV_TMR_INDEX_11 11 1702 #define DRV_TMR_INDEX_COUNT TMR_NUMBER_OF_MODULES 1787 uint32_t dividerMin ;
1789 uint32_t dividerMax ;
1792 uint32_t dividerStep ;
1808 SYS_MODULE_INIT moduleInit ;
1810 TMR_MODULE_ID tmrId ;
1814 TMR_PRESCALE prescale ;
1818 INT_SOURCE interruptSource ;
1826 bool asyncWriteEnable ;
1841 uint32_t alarmCount ) ;
1903 const SYS_MODULE_INDEX drvIndex ,
1904 const SYS_MODULE_INIT *
const init ) ;
1944 SYS_MODULE_OBJ
object ) ;
1991 SYS_MODULE_OBJ
object ) ;
2025 SYS_MODULE_OBJ
object ) ;
2079 const SYS_MODULE_INDEX index ,
2180 uint32_t counterPeriod ) ;
2670 TMR_PRESCALE preScale ) ;
2910 #ifndef _DRV_TMR_DEPRECATED_H 2911 #define _DRV_TMR_DEPRECATED_H 2952 #define DRV_TMR_Tasks_ISR( object ) DRV_TMR_Tasks ( object ) 3016 #define DRV_TMR_CounterValue16BitSet( handle , counterPeriod ) DRV_TMR_CounterValueSet ( handle , counterPeriod ) 3081 #define DRV_TMR_CounterValue32BitSet( handle , counterPeriod ) DRV_TMR_CounterValueSet ( handle , counterPeriod ) 3140 #define DRV_TMR_CounterValue16BitGet( handle ) DRV_TMR_CounterValueGet ( handle ) 3201 #define DRV_TMR_CounterValue32BitGet( handle ) DRV_TMR_CounterValueGet ( handle ) 3260 #define DRV_TMR_Alarm16BitRegister( handle , period , isPeriodic , context , callBack ) DRV_TMR_AlarmRegister ( handle , period , isPeriodic , context , callBack ) 3321 #define DRV_TMR_Alarm32BitRegister( handle , period , isPeriodic , context , callBack ) DRV_TMR_AlarmRegister ( handle , period , isPeriodic , context , callBack ) 3351 #define DRV_TMR_AlarmPeriod16BitSet( handle , value ) DRV_TMR_AlarmPeriodSet ( handle , value ) 3383 #define DRV_TMR_AlarmPeriod32BitSet( handle , period ) DRV_TMR_AlarmPeriodSet ( handle , period ) 3414 #define DRV_TMR_AlarmPeriod16BitGet( handle ) DRV_TMR_AlarmPeriodGet ( handle ) 3446 #define DRV_TMR_AlarmPeriod32BitGet( handle ) DRV_TMR_AlarmPeriodGet ( handle ) 3508 #define DRV_TMR_Alarm16BitDeregister( handle ) DRV_TMR_AlarmDeregister ( handle ) 3573 #define DRV_TMR_Alarm32BitDeregister( handle ) DRV_TMR_AlarmDeregister ( handle ) 3590 #include "peripheral/tmr/plib_tmr.h" 3591 #include "peripheral/int/plib_int.h" 3593 #define DRV_TIMER_DIVIDER_MAX_32BIT 0xffffffff 3595 #define DRV_TIMER_DIVIDER_MIN_32BIT 0x2 3597 #define DRV_TIMER_DIVIDER_MAX_16BIT 0x10000 3599 #define DRV_TIMER_DIVIDER_MIN_16BIT 0x2 3618 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 0)));
3624 static inline SYS_STATUS
3627 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 2)));
3638 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 4)));
3649 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 6)));
3659 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 8)));
3668 TMR_PRESCALE prescale ) ;
3699 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 10)));
3728 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 12)));
3734 static inline SYS_STATUS
3737 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 14)));
3748 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 16)));
3759 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 18)));
3769 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 20)));
3778 TMR_PRESCALE prescale ) ;
3809 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 22)));
3838 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 24)));
3844 static inline SYS_STATUS
3847 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 26)));
3858 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 28)));
3869 int izzqqzz=((int)(
bitmapstruct.element0 |= (1 << 30)));
3879 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 0)));
3888 TMR_PRESCALE prescale ) ;
3919 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 2)));
3948 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 4)));
3954 static inline SYS_STATUS
3957 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 6)));
3968 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 8)));
3979 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 10)));
3989 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 12)));
3998 TMR_PRESCALE prescale ) ;
4029 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 14)));
4058 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 16)));
4064 static inline SYS_STATUS
4067 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 18)));
4078 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 20)));
4089 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 22)));
4099 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 24)));
4108 TMR_PRESCALE prescale ) ;
4139 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 26)));
4158 #include "peripheral/int/plib_int.h" 4200 #ifndef _DRV_PMP_STATIC_H 4201 #define _DRV_PMP_STATIC_H 4202 #include "peripheral/pmp/plib_pmp.h" 4217 PMP_DATA_WAIT_STATES dataWait ,
4218 PMP_STROBE_WAIT_STATES strobeWait ,
4219 PMP_DATA_HOLD_STATES dataHold ) ;
4274 #ifndef _DRV_USART_STATIC_H 4275 #define _DRV_USART_STATIC_H 4314 #ifndef _DRV_USART_STATIC_LOCAL_H 4315 #define _DRV_USART_STATIC_LOCAL_H 4322 #include <stdbool.h> 4359 #ifndef _DRV_USART_H 4360 #define _DRV_USART_H 4400 #ifndef _DRV_USART_DEFINITIONS_H 4401 #define _DRV_USART_DEFINITIONS_H 4407 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 4408 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 4445 #ifndef _PLIB_USART_H 4446 #define _PLIB_USART_H 4489 #ifndef _USART_PROCESSOR_H 4490 #define _USART_PROCESSOR_H 4499 #include <stdbool.h> 4500 #error "No Processor Family specified" 4544 USART_MODULE_ID index ) ;
4574 USART_MODULE_ID index ) ;
4606 USART_MODULE_ID index ) ;
4640 USART_MODULE_ID index ,
4641 USART_BRG_CLOCK_SOURCE brgClockSource ) ;
4670 USART_BRG_CLOCK_SOURCE
4672 USART_MODULE_ID index ) ;
4726 USART_MODULE_ID index ) ;
4756 USART_MODULE_ID index ) ;
4785 USART_MODULE_ID index ) ;
4817 USART_MODULE_ID index ) ;
4848 USART_MODULE_ID index ) ;
4890 USART_MODULE_ID index ) ;
4923 USART_MODULE_ID index ) ;
4955 USART_MODULE_ID index ) ;
4996 USART_MODULE_ID index ,
4997 uint32_t clockFrequency ,
4998 uint32_t baudRate ) ;
5039 USART_MODULE_ID index ,
5040 uint32_t clockFrequency ,
5041 uint32_t baudRate ) ;
5074 USART_MODULE_ID index ,
5075 int32_t clockFrequency ) ;
5110 USART_MODULE_ID index ,
5145 USART_MODULE_ID index ) ;
5180 USART_MODULE_ID index ,
5215 USART_MODULE_ID index ) ;
5247 USART_MODULE_ID index ) ;
5281 USART_MODULE_ID index ) ;
5314 USART_MODULE_ID index ) ;
5347 USART_MODULE_ID index ) ;
5381 USART_MODULE_ID index ,
5426 USART_MODULE_ID index ) ;
5460 USART_MODULE_ID index ) ;
5496 USART_MODULE_ID index ) ;
5533 USART_MODULE_ID index ,
5573 USART_MODULE_ID index ) ;
5611 USART_MODULE_ID index ) ;
5646 USART_MODULE_ID index ) ;
5680 USART_MODULE_ID index ) ;
5714 USART_MODULE_ID index ) ;
5747 USART_MODULE_ID index ) ;
5779 USART_MODULE_ID index ) ;
5811 USART_MODULE_ID index ) ;
5844 USART_MODULE_ID index ) ;
5878 USART_MODULE_ID index ) ;
5907 USART_MODULE_ID index ) ;
5936 USART_MODULE_ID index ) ;
5968 USART_MODULE_ID index ) ;
6000 USART_MODULE_ID index ) ;
6030 USART_MODULE_ID index ) ;
6060 USART_MODULE_ID index ) ;
6089 USART_MODULE_ID index ) ;
6118 USART_MODULE_ID index ) ;
6152 USART_MODULE_ID index ,
6153 USART_TRANSMIT_INTR_MODE fifolevel ) ;
6185 USART_MODULE_ID index ,
6186 USART_RECEIVE_INTR_MODE interruptMode ) ;
6219 USART_MODULE_ID index ,
6220 USART_LINECONTROL_MODE dataFlowConfig ) ;
6253 USART_MODULE_ID index ,
6254 USART_HANDSHAKE_MODE handshakeConfig ) ;
6287 USART_MODULE_ID index ,
6318 USART_MODULE_ID index ) ;
6347 USART_MODULE_ID index ) ;
6378 USART_MODULE_ID index ) ;
6409 USART_MODULE_ID index ) ;
6439 USART_MODULE_ID index ) ;
6471 USART_MODULE_ID index ,
6472 USART_OPERATION_MODE operationmode ) ;
6502 USART_MODULE_ID index ) ;
6535 USART_MODULE_ID index ) ;
6564 USART_MODULE_ID index ) ;
6594 USART_MODULE_ID index ) ;
6630 USART_MODULE_ID index ) ;
6681 USART_MODULE_ID index ,
6684 bool wakeFromSleep ,
6729 USART_MODULE_ID index ,
6730 USART_RECEIVE_INTR_MODE receiveInterruptMode ,
6731 USART_TRANSMIT_INTR_MODE transmitInterruptMode ,
6732 USART_OPERATION_MODE operationMode ) ;
6778 USART_MODULE_ID index ,
6779 uint32_t systemClock ,
6825 USART_MODULE_ID index ) ;
6846 USART_MODULE_ID index ) ;
6867 USART_MODULE_ID index ) ;
6901 USART_MODULE_ID index ) ;
6928 USART_MODULE_ID index ) ;
6954 USART_MODULE_ID index ) ;
6981 USART_MODULE_ID index ) ;
7007 USART_MODULE_ID index ) ;
7032 USART_MODULE_ID index ) ;
7058 USART_MODULE_ID index ) ;
7083 USART_MODULE_ID index ) ;
7109 USART_MODULE_ID index ) ;
7134 USART_MODULE_ID index ) ;
7160 USART_MODULE_ID index ) ;
7187 USART_MODULE_ID index ) ;
7213 USART_MODULE_ID index ) ;
7239 USART_MODULE_ID index ) ;
7266 USART_MODULE_ID index ) ;
7293 USART_MODULE_ID index ) ;
7320 USART_MODULE_ID index ) ;
7346 USART_MODULE_ID index ) ;
7371 USART_MODULE_ID index ) ;
7397 USART_MODULE_ID index ) ;
7424 USART_MODULE_ID index ) ;
7450 USART_MODULE_ID index ) ;
7476 USART_MODULE_ID index ) ;
7501 USART_MODULE_ID index ) ;
7526 USART_MODULE_ID index ) ;
7551 USART_MODULE_ID index ) ;
7577 USART_MODULE_ID index ) ;
7602 USART_MODULE_ID index ) ;
7628 USART_MODULE_ID index ) ;
7654 USART_MODULE_ID index ) ;
7679 USART_MODULE_ID index ) ;
7705 USART_MODULE_ID index ) ;
7730 USART_MODULE_ID index ) ;
7755 USART_MODULE_ID index ) ;
7782 USART_MODULE_ID index ) ;
7807 USART_MODULE_ID index ) ;
7833 USART_MODULE_ID index ) ;
7898 #include "system/common/sys_common.h" 7899 #include "system/common/sys_module.h" 7911 #include "system/int/sys_int.h" 7983 #ifndef _SYS_DMA_DEFINITIONS_H 7984 #define _SYS_DMA_DEFINITIONS_H 7990 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 7991 #include "system/common/sys_common.h" 7992 #include "system/common/sys_module.h" 8062 #ifndef _PLIB_DMA_PROCESSOR_H 8063 #define _PLIB_DMA_PROCESSOR_H 8064 #error "Can't find header" 8108 DMA_MODULE_ID index ,
8109 DMA_CHANNEL channel ) ;
8143 DMA_MODULE_ID index ,
8144 DMA_CHANNEL channel ,
8145 DMA_CHANNEL_COLLISION collisonType ) ;
8177 DMA_MODULE_ID index ,
8178 DMA_CHANNEL channel ) ;
8210 DMA_MODULE_ID index ,
8211 DMA_CHANNEL channel ) ;
8249 DMA_MODULE_ID index ,
8250 DMA_CHANNEL channel ,
8251 DMA_CHANNEL_PRIORITY channelPriority ) ;
8280 DMA_CHANNEL_PRIORITY
8282 DMA_MODULE_ID index ,
8283 DMA_CHANNEL channel ) ;
8311 DMA_MODULE_ID index ,
8312 DMA_CHANNEL_PRIORITY channelPriority ) ;
8337 DMA_CHANNEL_PRIORITY
8339 DMA_MODULE_ID index ) ;
8369 DMA_MODULE_ID index ,
8370 DMA_CHANNEL channel ) ;
8401 DMA_MODULE_ID index ,
8402 DMA_CHANNEL channel ) ;
8431 DMA_MODULE_ID index ,
8432 DMA_CHANNEL channel ) ;
8461 DMA_MODULE_ID index ,
8462 DMA_CHANNEL channel ) ;
8493 DMA_MODULE_ID index ,
8494 DMA_CHANNEL channel ) ;
8523 DMA_MODULE_ID index ,
8524 DMA_CHANNEL channel ) ;
8555 DMA_MODULE_ID index ,
8556 DMA_CHANNEL channel ) ;
8587 DMA_MODULE_ID index ,
8588 DMA_CHANNEL channel ) ;
8617 DMA_MODULE_ID index ,
8618 DMA_CHANNEL channel ) ;
8649 DMA_MODULE_ID index ,
8650 DMA_CHANNEL channel ) ;
8679 DMA_MODULE_ID index ,
8680 DMA_CHANNEL channel ) ;
8710 DMA_MODULE_ID index ,
8711 DMA_CHANNEL channel ) ;
8741 DMA_MODULE_ID index ,
8742 DMA_CHANNEL channel ) ;
8772 DMA_MODULE_ID index ,
8773 DMA_CHANNEL channel ) ;
8803 DMA_MODULE_ID index ,
8804 DMA_CHANNEL channel ) ;
8835 DMA_MODULE_ID index ,
8836 DMA_CHANNEL channel ) ;
8867 DMA_MODULE_ID index ,
8868 DMA_CHANNEL channel ,
8869 DMA_CHANNEL_TRANSFER_DIRECTION chTransferDirection ) ;
8898 DMA_CHANNEL_TRANSFER_DIRECTION
8900 DMA_MODULE_ID index ,
8901 DMA_CHANNEL channel ) ;
8937 DMA_MODULE_ID index ,
8938 DMA_CHANNEL channel ,
8940 DMA_ADDRESS_OFFSET_TYPE offset ) ;
8973 DMA_MODULE_ID index ,
8974 DMA_CHANNEL channel ,
8975 DMA_ADDRESS_OFFSET_TYPE offset ) ;
9006 DMA_MODULE_ID index ,
9007 DMA_CHANNEL channel ,
9008 uint16_t peripheraladdress ) ;
9036 DMA_MODULE_ID index ,
9037 DMA_CHANNEL channel ) ;
9068 DMA_MODULE_ID index ,
9069 DMA_CHANNEL channel ,
9070 uint16_t transferCount ) ;
9098 DMA_MODULE_ID index ,
9099 DMA_CHANNEL channel ) ;
9132 DMA_MODULE_ID index ,
9133 DMA_CHANNEL channel ,
9134 DMA_SOURCE_ADDRESSING_MODE sourceAddressMode ) ;
9162 DMA_SOURCE_ADDRESSING_MODE
9164 DMA_MODULE_ID index ,
9165 DMA_CHANNEL channel ) ;
9198 DMA_MODULE_ID index ,
9199 DMA_CHANNEL channel ,
9200 DMA_DESTINATION_ADDRESSING_MODE destinationAddressMode ) ;
9229 DMA_DESTINATION_ADDRESSING_MODE
9231 DMA_MODULE_ID index ,
9232 DMA_CHANNEL channel ) ;
9265 DMA_MODULE_ID index ,
9266 DMA_CHANNEL channel ,
9267 DMA_CHANNEL_ADDRESSING_MODE channelAddressMode ) ;
9295 DMA_CHANNEL_ADDRESSING_MODE
9297 DMA_MODULE_ID index ,
9298 DMA_CHANNEL channel ) ;
9336 DMA_MODULE_ID index ,
9337 DMA_CHANNEL channel ,
9338 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9374 DMA_MODULE_ID index ,
9375 DMA_CHANNEL channel ,
9376 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9411 DMA_MODULE_ID index ,
9412 DMA_CHANNEL channel ,
9413 DMA_CHANNEL_TRIGGER_TYPE trigger ) ;
9442 DMA_CHANNEL_INT_SOURCE
9444 DMA_MODULE_ID index ,
9445 DMA_CHANNEL channel ) ;
9480 DMA_MODULE_ID index ,
9481 DMA_CHANNEL channel ,
9482 DMA_TRIGGER_SOURCE IRQnum ) ;
9517 DMA_MODULE_ID index ,
9518 DMA_CHANNEL channel ,
9519 DMA_TRIGGER_SOURCE IRQ ) ;
9550 DMA_MODULE_ID index ,
9551 DMA_CHANNEL channel ,
9552 DMA_CHANNEL_DATA_SIZE channelDataSize ) ;
9579 DMA_CHANNEL_DATA_SIZE
9581 DMA_MODULE_ID index ,
9582 DMA_CHANNEL channel ) ;
9616 DMA_MODULE_ID index ,
9617 DMA_CHANNEL channel ,
9618 DMA_TRANSFER_MODE channeltransferMode ) ;
9650 DMA_MODULE_ID index ,
9651 DMA_CHANNEL channel ) ;
9680 DMA_MODULE_ID index ,
9681 DMA_CHANNEL channel ) ;
9711 DMA_MODULE_ID index ,
9712 DMA_CHANNEL channel ) ;
9741 DMA_MODULE_ID index ,
9742 DMA_CHANNEL channel ) ;
9770 DMA_MODULE_ID index ,
9771 DMA_CHANNEL channel ) ;
9801 DMA_MODULE_ID index ,
9802 DMA_CHANNEL channel ) ;
9829 DMA_MODULE_ID index ,
9830 DMA_CHANNEL channel ) ;
9866 DMA_MODULE_ID index ,
9867 DMA_CHANNEL channel ) ;
9898 DMA_MODULE_ID index ,
9899 DMA_CHANNEL channel ) ;
9932 DMA_MODULE_ID index ) ;
9961 DMA_MODULE_ID index ) ;
9991 DMA_MODULE_ID index ) ;
10020 DMA_MODULE_ID index ) ;
10049 DMA_MODULE_ID index ) ;
10079 DMA_MODULE_ID index ) ;
10107 DMA_MODULE_ID index ) ;
10135 DMA_MODULE_ID index ) ;
10163 DMA_MODULE_ID index ) ;
10192 DMA_MODULE_ID index ) ;
10220 DMA_MODULE_ID index ) ;
10254 DMA_MODULE_ID index ) ;
10284 DMA_MODULE_ID index ) ;
10314 DMA_MODULE_ID index ) ;
10343 DMA_MODULE_ID index ) ;
10378 DMA_MODULE_ID index ,
10379 DMA_CHANNEL channel ) ;
10408 DMA_MODULE_ID index ) ;
10440 DMA_MODULE_ID index ,
10441 DMA_CRC_TYPE CRCType ) ;
10472 DMA_MODULE_ID index ) ;
10502 DMA_MODULE_ID index ) ;
10532 DMA_MODULE_ID index ) ;
10562 DMA_MODULE_ID index ) ;
10591 DMA_MODULE_ID index ) ;
10621 DMA_MODULE_ID index ) ;
10650 DMA_MODULE_ID index ) ;
10680 DMA_MODULE_ID index ,
10681 uint8_t polyLength ) ;
10710 DMA_MODULE_ID index ) ;
10739 DMA_MODULE_ID index ,
10740 DMA_CRC_BIT_ORDER bitOrder ) ;
10771 DMA_MODULE_ID index ) ;
10800 DMA_MODULE_ID index ) ;
10830 DMA_MODULE_ID index ,
10831 DMA_CRC_BYTE_ORDER byteOrder ) ;
10860 DMA_MODULE_ID index ) ;
10891 DMA_MODULE_ID index ) ;
10923 DMA_MODULE_ID index ,
10924 uint32_t DMACRCdata ) ;
10955 DMA_MODULE_ID index ) ;
10988 DMA_MODULE_ID index ,
10989 uint32_t DMACRCXOREnableMask ) ;
11027 DMA_MODULE_ID index ,
11028 DMA_CHANNEL dmaChannel ) ;
11065 DMA_MODULE_ID index ,
11066 DMA_CHANNEL dmaChannel ,
11067 uint32_t sourceStartAddress ) ;
11101 DMA_MODULE_ID index ,
11102 DMA_CHANNEL dmaChannel ) ;
11140 DMA_MODULE_ID index ,
11141 DMA_CHANNEL dmaChannel ,
11142 uint32_t destinationStartAddress ) ;
11182 DMA_MODULE_ID index ,
11183 DMA_CHANNEL dmaChannel ) ;
11222 DMA_MODULE_ID index ,
11223 DMA_CHANNEL dmaChannel ,
11224 uint16_t sourceSize ) ;
11259 DMA_MODULE_ID index ,
11260 DMA_CHANNEL dmaChannel ) ;
11297 DMA_MODULE_ID index ,
11298 DMA_CHANNEL dmaChannel ,
11299 uint16_t destinationSize ) ;
11333 DMA_MODULE_ID index ,
11334 DMA_CHANNEL dmaChannel ) ;
11369 DMA_MODULE_ID index ,
11370 DMA_CHANNEL dmaChannel ) ;
11405 DMA_MODULE_ID index ,
11406 DMA_CHANNEL dmaChannel ) ;
11443 DMA_MODULE_ID index ,
11444 DMA_CHANNEL dmaChannel ,
11445 uint16_t CellSize ) ;
11479 DMA_MODULE_ID index ,
11480 DMA_CHANNEL dmaChannel ) ;
11517 DMA_MODULE_ID index ,
11518 DMA_CHANNEL dmaChannel ) ;
11557 DMA_MODULE_ID index ,
11558 DMA_CHANNEL dmaChannel ,
11559 uint16_t patternData ) ;
11603 DMA_MODULE_ID index ,
11604 DMA_CHANNEL dmaChannel ,
11605 DMA_INT_TYPE dmaINTSource ) ;
11640 DMA_MODULE_ID index ,
11641 DMA_CHANNEL dmaChannel ,
11642 DMA_INT_TYPE dmaINTSource ) ;
11678 DMA_MODULE_ID index ,
11679 DMA_CHANNEL dmaChannel ,
11680 DMA_INT_TYPE dmaINTSource ) ;
11714 DMA_MODULE_ID index ,
11715 DMA_CHANNEL dmaChannel ,
11716 DMA_INT_TYPE dmaINTSource ) ;
11750 DMA_MODULE_ID index ,
11751 DMA_CHANNEL dmaChannel ,
11752 DMA_INT_TYPE dmaINTSource ) ;
11790 DMA_MODULE_ID index ,
11791 DMA_CHANNEL dmaChannel ,
11792 DMA_INT_TYPE dmaINTSource ) ;
11825 DMA_MODULE_ID index ,
11826 DMA_CHANNEL dmaChannel ,
11827 DMA_PATTERN_LENGTH patternLen ) ;
11860 DMA_MODULE_ID index ,
11861 DMA_CHANNEL dmaChannel ) ;
11891 DMA_MODULE_ID index ,
11892 DMA_CHANNEL channel ) ;
11925 DMA_MODULE_ID index ,
11926 DMA_CHANNEL channel ) ;
11956 DMA_MODULE_ID index ,
11957 DMA_CHANNEL channel ) ;
11989 DMA_MODULE_ID index ,
11990 DMA_CHANNEL channel ,
11991 uint8_t pattern ) ;
12022 DMA_MODULE_ID index ,
12023 DMA_CHANNEL channel ) ;
12055 DMA_MODULE_ID index ) ;
12080 DMA_MODULE_ID index ) ;
12104 DMA_MODULE_ID index ) ;
12129 DMA_MODULE_ID index ) ;
12152 DMA_MODULE_ID index ) ;
12176 DMA_MODULE_ID index ) ;
12199 DMA_MODULE_ID index ) ;
12223 DMA_MODULE_ID index ) ;
12247 DMA_MODULE_ID index ) ;
12272 DMA_MODULE_ID index ) ;
12296 DMA_MODULE_ID index ) ;
12320 DMA_MODULE_ID index ) ;
12343 DMA_MODULE_ID index ) ;
12367 DMA_MODULE_ID index ) ;
12391 DMA_MODULE_ID index ) ;
12415 DMA_MODULE_ID index ) ;
12439 DMA_MODULE_ID index ) ;
12463 DMA_MODULE_ID index ) ;
12486 DMA_MODULE_ID index ) ;
12511 DMA_MODULE_ID index ) ;
12536 DMA_MODULE_ID index ) ;
12560 DMA_MODULE_ID index ) ;
12585 DMA_MODULE_ID index ) ;
12609 DMA_MODULE_ID index ) ;
12633 DMA_MODULE_ID index ) ;
12659 DMA_MODULE_ID index ) ;
12684 DMA_MODULE_ID index ) ;
12708 DMA_MODULE_ID index ) ;
12733 DMA_MODULE_ID index ) ;
12756 DMA_MODULE_ID index ) ;
12779 DMA_MODULE_ID index ) ;
12802 DMA_MODULE_ID index ) ;
12825 DMA_MODULE_ID index ) ;
12850 DMA_MODULE_ID index ) ;
12875 DMA_MODULE_ID index ) ;
12899 DMA_MODULE_ID index ) ;
12924 DMA_MODULE_ID index ) ;
12948 DMA_MODULE_ID index ) ;
12972 DMA_MODULE_ID index ) ;
12995 DMA_MODULE_ID index ) ;
13018 DMA_MODULE_ID index ) ;
13042 DMA_MODULE_ID index ) ;
13066 DMA_MODULE_ID index ) ;
13090 DMA_MODULE_ID index ) ;
13117 #define DMA_CHANNEL_NONE ( ( DMA_CHANNEL ) - 1 ) 13130 #define DMA_CHANNEL_ANY ( ( DMA_CHANNEL ) - 2 ) 13143 #define SYS_DMA_CHANNEL_COUNT DMA_NUMBER_OF_CHANNELS 13173 #define SYS_DMA_CHANNEL_HANDLE_INVALID ( ( SYS_DMA_CHANNEL_HANDLE ) ( - 1 ) ) 13347 DMA_CRC_TYPE type ;
13353 uint8_t polyLength ;
13356 DMA_CRC_BIT_ORDER bitOrder ;
13359 DMA_CRC_BYTE_ORDER byteOrder ;
13369 uint32_t xorBitMask ;
13494 SYS_MODULE_OBJ
object ,
13495 DMA_CHANNEL activeChannel ) ;
13498 #define SYS_DMA_TasksISR( object , activeChannel ) SYS_DMA_Tasks ( object , activeChannel ) 13543 uintptr_t contextHandle ) ;
13589 const SYS_MODULE_INIT *
const init ) ;
13640 DMA_CHANNEL channel ) ;
13726 DMA_TRIGGER_SOURCE eventSrc ) ;
13804 DMA_PATTERN_LENGTH length ,
13806 uint8_t ignorePattern ) ;
14059 const void * srcAddr ,
14061 const void * destAddr ,
14063 size_t cellSize ) ;
14160 const void * srcAddr ,
14162 const void * destAddr ,
14164 size_t cellSize ) ;
14360 const uintptr_t contextHandle ) ;
14656 DMA_TRIGGER_SOURCE eventSrc ) ;
14835 SYS_MODULE_OBJ
object ,
14836 DMA_CHANNEL activeChannel ) ;
14846 SYS_MODULE_OBJ
object ) ;
14856 SYS_MODULE_OBJ
object ,
14857 DMA_CHANNEL activeChannel ) ;
14884 #define DRV_USART_INDEX_0 0 14885 #define DRV_USART_INDEX_1 1 14886 #define DRV_USART_INDEX_2 2 14887 #define DRV_USART_INDEX_3 3 14888 #define DRV_USART_INDEX_4 4 14889 #define DRV_USART_INDEX_5 5 14903 #define DRV_USART_COUNT USART_NUMBER_OF_MODULES 14914 #define DRV_USART_WRITE_ERROR ( ( uint32_t ) ( - 1 ) ) 14925 #define DRV_USART_READ_ERROR ( ( uint32_t ) ( - 1 ) ) 14959 #define DRV_USART_BUFFER_HANDLE_INVALID ( ( DRV_USART_BUFFER_HANDLE ) ( - 1 ) ) 15110 uintptr_t context ) ;
15158 USART_HANDSHAKE_MODE_FLOW_CONTROL
15162 USART_HANDSHAKE_MODE_SIMPLEX
15324 } AddressedModeInit ;
15349 = USART_ERROR_PARITY
15354 = USART_ERROR_FRAMING
15359 = USART_ERROR_RECEIVER_OVERRUN
15441 SYS_MODULE_INIT moduleInit ;
15445 USART_MODULE_ID usartID ;
15463 uint32_t brgClock ;
15479 USART_OPERATION_MODE linesEnable ;
15483 INT_SOURCE interruptTransmit ;
15487 INT_SOURCE interruptReceive ;
15491 INT_SOURCE interruptError ;
15496 unsigned int queueSizeReceive ;
15501 unsigned int queueSizeTransmit ;
15505 DMA_CHANNEL dmaChannelTransmit ;
15509 DMA_CHANNEL dmaChannelReceive ;
15513 INT_SOURCE dmaInterruptTransmit ;
15517 INT_SOURCE dmaInterruptReceive ;
15601 const SYS_MODULE_INDEX index ,
15602 const SYS_MODULE_INIT *
const init ) ;
15640 SYS_MODULE_OBJ
object ) ;
15678 SYS_MODULE_OBJ
object ) ;
15719 SYS_MODULE_OBJ
object ) ;
15760 SYS_MODULE_OBJ
object ) ;
15801 SYS_MODULE_OBJ
object ) ;
15880 const SYS_MODULE_INDEX index ,
16064 const size_t size ) ;
16257 const size_t size ) ;
16345 const uintptr_t context ) ;
16612 const size_t numbytes ) ;
16680 const size_t numbytes ) ;
16817 const uint8_t byte ) ;
17035 const SYS_MODULE_INDEX index ,
17088 const SYS_MODULE_INDEX index ,
17137 const SYS_MODULE_INDEX index ,
17352 #ifndef _DRV_USART_FEATURE_MAPPING_H 17353 #define _DRV_USART_FEATURE_MAPPING_H 17362 #define _DRV_USART_InterruptSourceIsEnabled( source ) false 17363 #define _DRV_USART_InterruptSourceEnable( source ) 17364 #define _DRV_USART_InterruptSourceDisable( source ) false 17365 #define _DRV_USART_InterruptSourceStatusClear( source ) SYS_INT_SourceStatusClear ( source ) 17366 #define _DRV_USART_SEM_POST( x ) OSAL_SEM_Post ( x ) 17367 #define _DRV_USART_TAKE_MUTEX( x , y ) OSAL_MUTEX_Lock ( x , y ) 17368 #define _DRV_USART_RELEASE_MUTEX( x ) OSAL_MUTEX_Unlock ( x ) 17369 #define _SYS_DMA_ChannelForceStart( channelHandle ) SYS_DMA_ChannelForceStart ( channelHandle ) 17372 #define _DRV_USART_ALWAYS_NON_BLOCKING ( DRV_IO_INTENT_NONBLOCKING ) 17381 #define _DRV_USART_TRANSMIT_BUFFER_QUEUE_TASKS( x ) _DRV_USART_ByteTransmitTasks ( x ) 17382 #define _DRV_USART_RECEIVE_BUFFER_QUEUE_TASKS( x ) _DRV_USART_ByteReceiveTasks ( x ) 17383 #define _DRV_USART_ERROR_TASKS( x ) _DRV_USART_ByteErrorTasks ( x ) 17384 #define _DRV_USART_CLIENT_BUFFER_QUEUE_OBJECTS_REMOVE( x ) true 17385 #define _DRV_USART_ByteModelInterruptSourceEnable( source ) 17398 #include "system/clk/sys_clk.h" 17399 #include "system/int/sys_int.h" 17437 #ifndef _SYS_DEBUG_H 17438 #define _SYS_DEBUG_H 17439 #include "C:\microchip\harmony\v2_06\framework\system\system.h" 17442 #define SYS_DEBUG_BUFFER_DMA_READY 17492 #define SYS_DEBUG_INDEX_0 0 17508 SYS_MODULE_INIT moduleInit ;
17512 SYS_MODULE_INDEX consoleIndex ;
17560 const SYS_MODULE_INDEX index ,
17561 const SYS_MODULE_INIT *
const init ) ;
17601 SYS_MODULE_OBJ
object ,
17602 const SYS_MODULE_INIT *
const init ) ;
17632 SYS_MODULE_OBJ
object ) ;
17665 SYS_MODULE_OBJ
object ) ;
17709 SYS_MODULE_OBJ
object ) ;
17752 const char * message ) ;
17802 const char * format ,
17892 #define _SYS_DEBUG_MESSAGE( level , message ) do { if ( ( level ) <= SYS_DEBUG_ErrorLevelGet ( ) ) SYS_DEBUG_Message ( message ) ; } while ( 0 ) 17936 #define _SYS_DEBUG_PRINT( level , format ,... ) do { if ( ( level ) <= SYS_DEBUG_ErrorLevelGet ( ) ) SYS_DEBUG_Print ( format , ## __VA_ARGS__ ) ; } while ( 0 ) 17979 #define SYS_MESSAGE( message ) 18012 #define SYS_DEBUG_MESSAGE( level , message ) 18059 #define SYS_PRINT( fmt ,... ) 18107 #define SYS_DEBUG_PRINT( level , fmt ,... ) 18132 #define SYS_DEBUG_BreakPoint( ) 18141 #define SYS_DEBUG( level , message ) SYS_DEBUG_MESSAGE ( level , message ) 18142 #define SYS_ERROR( level , fmt ,... ) SYS_DEBUG_PRINT ( level , fmt , ## __VA_ARGS__ ) 18143 #define SYS_ERROR_PRINT( level , fmt ,... ) SYS_DEBUG_PRINT ( level , fmt , ## __VA_ARGS__ ) 18160 #define _DRV_USART_RX_DEPTH 9 18226 const SYS_MODULE_INDEX index ,
18251 const uint8_t byte ) ;
18322 #ifndef _SYS_PORTS_H 18323 #define _SYS_PORTS_H 18362 #ifndef _SYS_PORTS_DEFINITIONS_H 18363 #define _SYS_PORTS_DEFINITIONS_H 18369 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 18370 #include "system/common/sys_common.h" 18371 #include "system/common/sys_module.h" 18408 #ifndef _PLIB_PORTS_H 18409 #define _PLIB_PORTS_H 18410 #include <stdint.h> 18411 #include <stddef.h> 18476 #ifndef _PLIB_PORTS_PROCESSOR_H 18477 #define _PLIB_PORTS_PROCESSOR_H 18478 #error "Can't find header" 18528 PORTS_MODULE_ID index ,
18529 PORTS_REMAP_INPUT_FUNCTION inputFunction ,
18530 PORTS_REMAP_INPUT_PIN remapInputPin ) ;
18573 PORTS_MODULE_ID index ,
18574 PORTS_REMAP_OUTPUT_FUNCTION outputFunction ,
18575 PORTS_REMAP_OUTPUT_PIN remapOutputPin ) ;
18610 PORTS_MODULE_ID index ,
18611 PORTS_ANALOG_PIN pin ,
18612 PORTS_PIN_MODE mode ) ;
18652 PORTS_MODULE_ID index ,
18653 PORTS_CHANNEL channel ,
18654 PORTS_BIT_POS bitPos ,
18655 PORTS_PIN_MODE mode ) ;
18690 PORTS_MODULE_ID index ,
18691 PORTS_CHANNEL channel ,
18692 PORTS_BIT_POS bitPos ) ;
18726 PORTS_MODULE_ID index ,
18727 PORTS_CHANNEL channel ,
18728 PORTS_BIT_POS bitPos ) ;
18765 PORTS_MODULE_ID index ,
18766 PORTS_CHANNEL channel ,
18767 PORTS_BIT_POS bitPos ) ;
18808 PORTS_MODULE_ID index ,
18809 PORTS_CHANNEL channel ,
18810 PORTS_BIT_POS bitPos ) ;
18849 PORTS_MODULE_ID index ,
18850 PORTS_CHANNEL channel ,
18851 PORTS_BIT_POS bitPos ) ;
18889 PORTS_MODULE_ID index ,
18890 PORTS_CHANNEL channel ,
18891 PORTS_BIT_POS bitPos ) ;
18926 PORTS_MODULE_ID index ,
18927 PORTS_CHANNEL channel ) ;
18962 PORTS_MODULE_ID index ,
18963 PORTS_CHANNEL channel ) ;
19000 PORTS_MODULE_ID index ,
19001 PORTS_CHANNEL channel ) ;
19038 PORTS_MODULE_ID index ,
19039 PORTS_CHANNEL channel ) ;
19076 PORTS_MODULE_ID index ,
19077 PORTS_CHANNEL channel ,
19078 PORTS_BIT_POS bitPos ) ;
19115 PORTS_MODULE_ID index ,
19116 PORTS_CHANNEL channel ,
19117 PORTS_BIT_POS bitPos ) ;
19155 PORTS_MODULE_ID index ,
19156 PORTS_CHANNEL channel ,
19157 PORTS_BIT_POS bitPos ) ;
19194 PORTS_MODULE_ID index ,
19195 PORTS_CHANNEL channel ,
19196 PORTS_BIT_POS bitPos ,
19231 PORTS_MODULE_ID index ,
19232 PORTS_CHANNEL channel ,
19233 PORTS_BIT_POS bitPos ) ;
19267 PORTS_MODULE_ID index ,
19268 PORTS_CHANNEL channel ,
19269 PORTS_BIT_POS bitPos ) ;
19303 PORTS_MODULE_ID index ,
19304 PORTS_CHANNEL channel ,
19305 PORTS_BIT_POS bitPos ) ;
19340 PORTS_MODULE_ID index ,
19341 PORTS_CHANNEL channel ,
19342 PORTS_BIT_POS bitPos ) ;
19377 PORTS_MODULE_ID index ,
19378 PORTS_CHANNEL channel ,
19379 PORTS_BIT_POS bitPos ) ;
19413 PORTS_MODULE_ID index ,
19414 PORTS_CHANNEL channel ,
19415 PORTS_BIT_POS bitPos ) ;
19449 PORTS_MODULE_ID index ,
19450 PORTS_CHANNEL channel ,
19451 PORTS_BIT_POS bitPos ) ;
19489 PORTS_MODULE_ID index ,
19490 PORTS_CHANNEL channel ) ;
19524 PORTS_MODULE_ID index ,
19525 PORTS_CHANNEL channel ) ;
19559 PORTS_MODULE_ID index ,
19560 PORTS_CHANNEL channel ,
19603 PORTS_MODULE_ID index ,
19604 PORTS_CHANNEL channel ,
19640 PORTS_MODULE_ID index ,
19641 PORTS_CHANNEL channel ,
19676 PORTS_MODULE_ID index ,
19677 PORTS_CHANNEL channel ,
19713 PORTS_MODULE_ID index ,
19714 PORTS_CHANNEL channel ,
19749 PORTS_MODULE_ID index ,
19750 PORTS_CHANNEL channel ,
19783 PORTS_MODULE_ID index ,
19784 PORTS_CHANNEL channel ) ;
19818 PORTS_MODULE_ID index ,
19819 PORTS_CHANNEL channel ,
19855 PORTS_MODULE_ID index ,
19856 PORTS_CHANNEL channel ,
19902 PORTS_MODULE_ID index ,
19903 PORTS_CHANNEL channel ,
19905 PORTS_PIN_MODE mode ) ;
19947 PORTS_MODULE_ID index ,
19948 PORTS_CHANNEL channel ,
19991 PORTS_MODULE_ID index ,
19992 PORTS_CHANNEL channel ,
20032 PORTS_MODULE_ID index ,
20033 PORTS_CHANNEL channel ,
20073 PORTS_MODULE_ID index ,
20074 PORTS_CHANNEL channel ,
20118 PORTS_MODULE_ID index ,
20119 PORTS_CHANNEL channel ,
20163 PORTS_MODULE_ID index ,
20164 PORTS_CHANNEL channel ,
20210 PORTS_MODULE_ID index ,
20211 PORTS_AN_PIN anPins ,
20212 PORTS_PIN_MODE mode ) ;
20255 PORTS_MODULE_ID index ,
20256 PORTS_CN_PIN cnPins ) ;
20300 PORTS_MODULE_ID index ,
20301 PORTS_CN_PIN cnPins ) ;
20344 PORTS_MODULE_ID index ,
20345 PORTS_CN_PIN cnPins ) ;
20388 PORTS_MODULE_ID index ,
20389 PORTS_CN_PIN cnPins ) ;
20423 PORTS_MODULE_ID index ) ;
20456 PORTS_MODULE_ID index ) ;
20492 PORTS_MODULE_ID index ,
20493 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20529 PORTS_MODULE_ID index ,
20530 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20567 PORTS_MODULE_ID index ) ;
20601 PORTS_MODULE_ID index ) ;
20637 PORTS_MODULE_ID index ,
20638 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20674 PORTS_MODULE_ID index ,
20675 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
20720 PORTS_MODULE_ID index ,
20721 PORTS_CHANNEL channel ,
20723 PORTS_PIN_SLEW_RATE slewRate ) ;
20760 PORTS_PIN_SLEW_RATE
20762 PORTS_MODULE_ID index ,
20763 PORTS_CHANNEL channel ,
20764 PORTS_BIT_POS bitPos ) ;
20803 PORTS_MODULE_ID index ,
20804 PORTS_CHANNEL channel ,
20805 PORTS_CHANGE_NOTICE_METHOD changeNoticeMethod ) ;
20838 PORTS_CHANGE_NOTICE_METHOD
20840 PORTS_MODULE_ID index ,
20841 PORTS_CHANNEL channel ) ;
20889 PORTS_MODULE_ID index ,
20890 PORTS_CHANNEL channel ,
20940 PORTS_MODULE_ID index ,
20941 PORTS_CHANNEL channel ,
20989 PORTS_MODULE_ID index ,
20990 PORTS_CHANNEL channel ,
20991 PORTS_BIT_POS bitPos ,
20992 PORTS_CHANGE_NOTICE_EDGE cnEdgeType ) ;
21035 PORTS_MODULE_ID index ,
21036 PORTS_CHANNEL channel ,
21037 PORTS_BIT_POS bitPos ) ;
21068 PORTS_MODULE_ID index ) ;
21092 PORTS_MODULE_ID index ) ;
21116 PORTS_MODULE_ID index ) ;
21140 PORTS_MODULE_ID index ) ;
21165 PORTS_MODULE_ID index ) ;
21190 PORTS_MODULE_ID index ) ;
21221 PORTS_MODULE_ID index ) ;
21249 PORTS_MODULE_ID index ) ;
21276 PORTS_MODULE_ID index ) ;
21301 PORTS_MODULE_ID index ) ;
21328 PORTS_MODULE_ID index ) ;
21353 PORTS_MODULE_ID index ) ;
21380 PORTS_MODULE_ID index ) ;
21405 PORTS_MODULE_ID index ) ;
21433 PORTS_MODULE_ID index ) ;
21461 PORTS_MODULE_ID index ) ;
21489 PORTS_MODULE_ID index ) ;
21515 PORTS_MODULE_ID index ) ;
21541 PORTS_MODULE_ID index ) ;
21567 PORTS_MODULE_ID index ) ;
21592 PORTS_MODULE_ID index ) ;
21618 PORTS_MODULE_ID index ) ;
21645 PORTS_MODULE_ID index ) ;
21670 PORTS_MODULE_ID index ) ;
21705 #ifndef _PLIB_PORTS_COMPATIBILITY_H 21706 #define _PLIB_PORTS_COMPATIBILITY_H 21707 #include <stdint.h> 21708 #include <stddef.h> 21743 #define PLIB_PORTS_ChangeNoticePerPortHasOccured PLIB_PORTS_ChangeNoticePerPortHasOccurred 21760 #include "system/int/sys_int.h" 21894 PORTS_MODULE_ID index ,
21895 PORTS_CHANNEL channel ) ;
21927 PORTS_MODULE_ID index ,
21928 PORTS_CHANNEL channel ,
21958 PORTS_MODULE_ID index ,
21959 PORTS_CHANNEL channel ) ;
21997 PORTS_MODULE_ID index ,
21998 PORTS_CHANNEL channel ,
22032 PORTS_MODULE_ID index ,
22033 PORTS_CHANNEL channel ,
22070 PORTS_MODULE_ID index ,
22072 PORTS_CHANNEL channel ,
22102 PORTS_MODULE_ID index ,
22103 PORTS_CHANNEL channel ) ;
22134 PORTS_MODULE_ID index ,
22135 PORTS_CHANNEL channel ,
22167 PORTS_MODULE_ID index ,
22168 PORTS_CHANNEL channel ,
22200 PORTS_MODULE_ID index ,
22201 PORTS_CHANNEL channel ,
22235 PORTS_MODULE_ID index ,
22236 PORTS_CHANNEL channel ) ;
22276 PORTS_MODULE_ID index ,
22277 PORTS_REMAP_INPUT_FUNCTION
function ,
22278 PORTS_REMAP_INPUT_PIN remapPin ) ;
22313 PORTS_MODULE_ID index ,
22314 PORTS_REMAP_OUTPUT_FUNCTION
function ,
22315 PORTS_REMAP_OUTPUT_PIN remapPin ) ;
22348 PORTS_MODULE_ID index ) ;
22376 PORTS_MODULE_ID index ) ;
22410 PORTS_MODULE_ID index ,
22411 PORTS_CHANGE_NOTICE_PIN pinNum ,
22443 PORTS_MODULE_ID index ,
22444 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
22473 PORTS_MODULE_ID index ) ;
22502 PORTS_MODULE_ID index ) ;
22533 PORTS_MODULE_ID index ,
22534 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
22565 PORTS_MODULE_ID index ,
22566 PORTS_CHANGE_NOTICE_PIN pinNum ) ;
22605 PORTS_MODULE_ID index ,
22606 PORTS_ANALOG_PIN pin ,
22607 PORTS_PIN_MODE mode ) ;
22644 PORTS_MODULE_ID index ,
22645 PORTS_CHANNEL channel ,
22646 PORTS_BIT_POS bitPos ,
22681 PORTS_MODULE_ID index ,
22682 PORTS_CHANNEL channel ,
22683 PORTS_BIT_POS bitPos ) ;
22716 PORTS_MODULE_ID index ,
22717 PORTS_CHANNEL channel ,
22718 PORTS_BIT_POS bitPos ) ;
22751 PORTS_MODULE_ID index ,
22752 PORTS_CHANNEL channel ,
22753 PORTS_BIT_POS bitPos ) ;
22786 PORTS_MODULE_ID index ,
22787 PORTS_CHANNEL channel ,
22788 PORTS_BIT_POS bitPos ) ;
22821 PORTS_MODULE_ID index ,
22822 PORTS_CHANNEL channel ,
22823 PORTS_BIT_POS bitPos ) ;
22860 PORTS_MODULE_ID index ,
22862 PORTS_CHANNEL channel ,
22863 PORTS_BIT_POS bitPos ) ;
22896 PORTS_MODULE_ID index ,
22897 PORTS_CHANNEL channel ,
22898 PORTS_BIT_POS bitPos ) ;
22931 PORTS_MODULE_ID index ,
22932 PORTS_CHANNEL channel ,
22933 PORTS_BIT_POS bitPos ) ;
22966 PORTS_MODULE_ID index ,
22967 PORTS_CHANNEL channel ,
22968 PORTS_BIT_POS bitPos ) ;
23001 PORTS_MODULE_ID index ,
23002 PORTS_CHANNEL channel ,
23003 PORTS_BIT_POS bitPos ) ;
23036 PORTS_MODULE_ID index ,
23037 PORTS_CHANNEL channel ,
23038 PORTS_BIT_POS bitPos ) ;
23071 PORTS_MODULE_ID index ,
23072 PORTS_CHANNEL channel ,
23073 PORTS_BIT_POS bitPos ) ;
23106 PORTS_MODULE_ID index ,
23107 PORTS_CHANNEL channel ,
23108 PORTS_BIT_POS bitPos ,
23191 #ifndef _DRV_SPI_DEFINITIONS_H 23192 #define _DRV_SPI_DEFINITIONS_H 23198 #include <stdint.h> 23199 #include <stdbool.h> 23200 #include "C:\microchip\harmony\v2_06\apps\Panel_Interface_Board\firmware\src\system_config\default\system_config.h" 23201 #include "C:\microchip\harmony\v2_06\framework\driver\driver_common.h" 23237 #ifndef _PLIB_SPI_H 23238 #define _PLIB_SPI_H 23272 #ifndef _PLIB_SPI_PROCESSOR_H 23273 #define _PLIB_SPI_PROCESSOR_H 23274 #error "Can't find header" 23319 SPI_MODULE_ID index ) ;
23349 SPI_MODULE_ID index ) ;
23381 SPI_MODULE_ID index ) ;
23413 SPI_MODULE_ID index ) ;
23447 SPI_MODULE_ID index ) ;
23477 SPI_MODULE_ID index ) ;
23514 SPI_MODULE_ID index ) ;
23553 SPI_MODULE_ID index ) ;
23583 SPI_MODULE_ID index ,
23614 SPI_MODULE_ID index ,
23648 SPI_MODULE_ID index ,
23649 SPI_COMMUNICATION_WIDTH width ) ;
23684 SPI_MODULE_ID index ,
23685 SPI_AUDIO_COMMUNICATION_WIDTH mode ) ;
23717 SPI_MODULE_ID index ,
23718 SPI_INPUT_SAMPLING_PHASE phase ) ;
23750 SPI_MODULE_ID index ,
23751 SPI_OUTPUT_DATA_PHASE phase ) ;
23782 SPI_MODULE_ID index ,
23783 SPI_CLOCK_POLARITY polarity ) ;
23813 SPI_MODULE_ID index ) ;
23843 SPI_MODULE_ID index ) ;
23881 SPI_MODULE_ID index ,
23882 uint32_t clockFrequency ,
23883 uint32_t baudRate ) ;
23914 SPI_MODULE_ID index ) ;
23946 SPI_MODULE_ID index ) ;
23979 SPI_MODULE_ID index ) ;
24012 SPI_MODULE_ID index ) ;
24044 SPI_MODULE_ID index ) ;
24074 SPI_MODULE_ID index ) ;
24105 SPI_MODULE_ID index ) ;
24136 SPI_MODULE_ID index ) ;
24167 SPI_MODULE_ID index ) ;
24199 SPI_MODULE_ID index ,
24200 SPI_FIFO_TYPE type ) ;
24232 SPI_MODULE_ID index ) ;
24264 SPI_MODULE_ID index ) ;
24298 SPI_MODULE_ID index ,
24299 SPI_FIFO_INTERRUPT mode ) ;
24329 SPI_MODULE_ID index ) ;
24359 SPI_MODULE_ID index ) ;
24391 SPI_MODULE_ID index ,
24392 SPI_FRAME_PULSE_DIRECTION direction ) ;
24425 SPI_MODULE_ID index ,
24426 SPI_FRAME_PULSE_POLARITY polarity ) ;
24459 SPI_MODULE_ID index ,
24460 SPI_FRAME_PULSE_EDGE edge ) ;
24493 SPI_MODULE_ID index ,
24494 SPI_FRAME_PULSE_WIDTH width ) ;
24528 SPI_MODULE_ID index ,
24529 SPI_FRAME_SYNC_PULSE pulse ) ;
24561 SPI_MODULE_ID index ) ;
24591 SPI_MODULE_ID index ) ;
24623 SPI_MODULE_ID index ) ;
24653 SPI_MODULE_ID index ) ;
24683 SPI_MODULE_ID index ) ;
24713 SPI_MODULE_ID index ) ;
24744 SPI_MODULE_ID index ,
24776 SPI_MODULE_ID index ,
24808 SPI_MODULE_ID index ,
24831 SPI_MODULE_ID index ) ;
24862 SPI_MODULE_ID index ,
24863 SPI_BAUD_RATE_CLOCK type ) ;
24895 SPI_MODULE_ID index ,
24896 SPI_ERROR_INTERRUPT error ) ;
24928 SPI_MODULE_ID index ,
24929 SPI_ERROR_INTERRUPT error ) ;
24960 SPI_MODULE_ID index ,
24961 SPI_AUDIO_ERROR error ) ;
24992 SPI_MODULE_ID index ,
24993 SPI_AUDIO_ERROR error ) ;
25023 SPI_MODULE_ID index ) ;
25053 SPI_MODULE_ID index ) ;
25085 SPI_MODULE_ID index ,
25086 SPI_AUDIO_TRANSMIT_MODE mode ) ;
25118 SPI_MODULE_ID index ,
25119 SPI_AUDIO_PROTOCOL mode ) ;
25152 SPI_MODULE_ID index ) ;
25178 SPI_MODULE_ID index ) ;
25204 SPI_MODULE_ID index ) ;
25229 SPI_MODULE_ID index ) ;
25254 SPI_MODULE_ID index ) ;
25279 SPI_MODULE_ID index ) ;
25305 SPI_MODULE_ID index ) ;
25330 SPI_MODULE_ID index ) ;
25355 SPI_MODULE_ID index ) ;
25380 SPI_MODULE_ID index ) ;
25405 SPI_MODULE_ID index ) ;
25430 SPI_MODULE_ID index ) ;
25456 SPI_MODULE_ID index ) ;
25481 SPI_MODULE_ID index ) ;
25506 SPI_MODULE_ID index ) ;
25531 SPI_MODULE_ID index ) ;
25557 SPI_MODULE_ID index ) ;
25583 SPI_MODULE_ID index ) ;
25609 SPI_MODULE_ID index ) ;
25633 SPI_MODULE_ID index ) ;
25658 SPI_MODULE_ID index ) ;
25683 SPI_MODULE_ID index ) ;
25708 SPI_MODULE_ID index ) ;
25734 SPI_MODULE_ID index ) ;
25759 SPI_MODULE_ID index ) ;
25784 SPI_MODULE_ID index ) ;
25809 SPI_MODULE_ID index ) ;
25834 SPI_MODULE_ID index ) ;
25859 SPI_MODULE_ID index ) ;
25885 SPI_MODULE_ID index ) ;
25912 SPI_MODULE_ID index ) ;
25937 SPI_MODULE_ID index ) ;
25963 SPI_MODULE_ID index ) ;
25989 SPI_MODULE_ID index ) ;
26015 SPI_MODULE_ID index ) ;
26040 SPI_MODULE_ID index ) ;
26065 SPI_MODULE_ID index ) ;
26091 SPI_MODULE_ID index ) ;
26117 SPI_MODULE_ID index ) ;
26129 #include "system/common/sys_common.h" 26130 #include "system/common/sys_module.h" 26131 #include "system/int/sys_int.h" 26132 #include "system/clk/sys_clk.h" 26133 #include "C:\microchip\harmony\v2_06\framework\system\ports\sys_ports.h" 26171 #define DRV_SPI_BUFFER_HANDLE_INVALID ( ( DRV_SPI_BUFFER_HANDLE ) ( - 1 ) ) 26183 #define DRV_SPI_INDEX_0 0 26184 #define DRV_SPI_INDEX_1 1 26185 #define DRV_SPI_INDEX_2 2 26186 #define DRV_SPI_INDEX_3 3 26187 #define DRV_SPI_INDEX_4 4 26188 #define DRV_SPI_INDEX_5 5 26200 #define DRV_SPI_INDEX_COUNT SPI_NUMBER_OF_MODULES 26449 SPI_MODULE_ID
spiId ;
26482 CLK_BUSES_PERIPHERAL
spiClk ;
26642 const SYS_MODULE_INDEX index ,
26643 const SYS_MODULE_INIT *
const init ) ;
26685 SYS_MODULE_OBJ
object ) ;
26734 SYS_MODULE_OBJ
object ) ;
26775 SYS_MODULE_OBJ
object ) ;
26840 const SYS_MODULE_INDEX drvIndex ,
27435 #include "driver/usb/usbhs/drv_usbhs.h" 27436 #include "usb/usb_device.h" 27464 #include <stdint.h> 27484 uint8_t RevNumber ;
27571 SYS_MODULE_OBJ sysTmr ;
27572 SYS_MODULE_OBJ drvTmr0 ;
27573 SYS_MODULE_OBJ drvTmr1 ;
27574 SYS_MODULE_OBJ drvTmr2 ;
27575 SYS_MODULE_OBJ drvTmr3 ;
27576 SYS_MODULE_OBJ drvTmr4 ;
27577 SYS_MODULE_OBJ drvUsart0 ;
27578 SYS_MODULE_OBJ drvPMP0 ;
27580 SYS_MODULE_OBJ spiObjectIdx0 ;
27582 SYS_MODULE_OBJ spiObjectIdx1 ;
27584 SYS_MODULE_OBJ spiObjectIdx2 ;
27585 SYS_MODULE_OBJ drvUSBObject ;
27586 SYS_MODULE_OBJ usbDevObject0 ;
27606 #include <stdbool.h> 27615 #define NEGATIVE_OFFSET 0x02U 27616 #define POS_HIGH_OFFSET 0x01U 27617 #define POS_LOW_OFFSET 0x03U 27618 #define DEFAULT_OFFSET 0x04U 27619 #define I_ARRAY_SIZE 50U 27666 uint16_t voltage_limit ;
27667 uint16_t upper_voltage_limit ;
27668 uint16_t volt_count ;
27670 uint16_t max_current ;
27671 uint16_t current_limit ;
27672 uint16_t upper_current_limit ;
27673 uint8_t over_current_count ;
27674 uint8_t array_sum_count ;
27675 uint8_t array_count ;
27677 int16_t i_array [ 50U ] ;
27679 bool new_current_values_flag ;
27680 bool new_voltage_values_flag ;
27681 bool overcurrent_flag ;
27682 bool overvoltage_flag ;
27683 uint16_t sensor_offset ;
27684 uint16_t sensor_constant ;
27685 bool sensor_offset_tick ;
27686 uint16_t v_array [ 50 ] ;
27687 uint16_t v_array_count ;
27693 uint8_t overvoltage_count ;
27821 #include <stdint.h> 27822 #include <stdbool.h> 27862 uint16_t hvps_cont ;
27863 uint16_t wl_cps_i ;
27864 uint16_t wl_cps_v ;
27865 uint16_t wl_sps_i_cf ;
27866 uint16_t wl_sps_i ;
27937 #include <stdint.h> 27938 #include <stdbool.h> 27944 #define S3_NUM_OF_POSITIONS 5U 27945 #define S6_NUM_OF_POSITIONS 3U 27946 #define S4_NUM_OF_POSITIONS 2U 27947 #define S1_NUM_OF_POSITIONS 2U 27987 uint8_t knob_switch_S3 [ 5 ] ;
27988 uint8_t key_switch_S6 [ 3 ] ;
27989 uint8_t pol_switch_S4 [ 2 ] ;
27990 uint8_t dump_fire_switch_S7 ;
27991 uint8_t fire_switch_S1 [ 2 ] ;
27992 uint8_t hvps_switch_S5 ;
27997 uint16_t store_buffer [ 2 ] ;
27998 uint16_t settings ;
27999 uint8_t dump_fire_count ;
28000 bool debounce_flag ;
28001 bool debounce_tick ;
28105 bool dmpfire_flag ;
28284 #include <stdbool.h> 28285 #include <stdint.h> 28317 uint8_t bitposn ) ;
28343 uint8_t bitposn ) ;
28414 #include <stdbool.h> 28454 int izzqqzz=((int)(
bitmapstruct.element1 |= (1 << 28)));
28479 4096.0F ) * ( 1.3243F /
28481 * 1000.0F * .650F ) ) ;
28677 int QZZZ = ((int)(
bitmapstruct.element3 |= (1 << 0)));
28898 int izzqqzz=((int)(
bitmapstruct.element4 |= (1 << 6)));
28934 int izzqqzz=((int)(
bitmapstruct.element4 |= (1 << 11)));
28980 #define qqqbranches 150 28981 #define QQQMAXMCDCSIZE 2 28985 #define ldra_sscanf 29001 #undef qqnull_params 29002 #define qqnull_params void 29004 #define qqzzidfield 1 29010 #define QQQFIXEDSIZE 29030 qqcptr = qqscan_str;
29032 while (qqcptr[0] ==
' ')
29038 if (qqcptr[0] ==
'-')
29044 while ((qqcptr[0] >=
'0') && (qqcptr[0] <=
'9'))
29046 qqvalue = 10 * qqvalue;
29047 qqvalue = qqvalue + (qqcptr[0] -
'0');
29050 qqvalue = qqisign * qqvalue;
29076 ldra_sprintf2 (&ldra_buffer[0], s,i,
zzfileid);
29077 ldra_port_write (&ldra_buffer[0]);
29085 ldra_port_write(s);
29093 ldra_sprintf2 (&ldra_buffer[0], s, i, j);
29094 ldra_port_write (&ldra_buffer[0]);
29102 ldra_sprintf3 (&ldra_buffer[0], s, i, j, k);
29103 ldra_port_write (&ldra_buffer[0]);
29111 ldra_sprintf4 (&ldra_buffer[0], s, i, j, k, l);
29112 ldra_port_write (&ldra_buffer[0]);
29231 static int branches_printed = 0;
29235 ldra_sprintf1 (&ldra_buffer[0], s, (i >> last) & ~(~0 << 8));
29236 ldra_port_write (&ldra_buffer[0]);
29237 ldra_sprintf1 (&ldra_buffer[0],
"%8d\n",
zzfileid );
29238 ldra_port_write (&ldra_buffer[0]);
29240 branches_printed += 8;
29260 #define ELEMENT(N) qqbmsoutput("%8d", bitmapstruct.element##N); 29261 #define LASTELEMENT 29262 #include "wl_sps_50zbelem.def"
void SYS_DMA_ChannelTransferEventHandlerSet(SYS_DMA_CHANNEL_HANDLE handle, const SYS_DMA_CHANNEL_TRANSFER_EVENT_HANDLER eventHandler, const uintptr_t contextHandle)
uint8_t PLIB_USART_AddressMaskGet(USART_MODULE_ID index)
DRV_HANDLE DRV_USART_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT ioIntent)
bool DRV_TMR2_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
uint16_t PLIB_DMA_ChannelXSourceSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void PLIB_USART_LoopbackDisable(USART_MODULE_ID index)
void PLIB_PORTS_RemapOutput(PORTS_MODULE_ID index, PORTS_REMAP_OUTPUT_FUNCTION outputFunction, PORTS_REMAP_OUTPUT_PIN remapOutputPin)
bool PLIB_DMA_ExistsBusy(DMA_MODULE_ID index)
DRV_TMR_OPERATION_MODE DRV_TMR2_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
SPI_BAUD_RATE_CLOCK baudClockSource
bool DRV_TMR3_Start(void)
unsigned int DRV_USART_TransmitBufferSizeGet(const DRV_HANDLE handle)
void PLIB_PORTS_ChangeNoticeInIdlePerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool DRV_TMR0_Start(void)
bool PLIB_DMA_ExistsCRCBitOrder(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXDestinationSize(DMA_MODULE_ID index)
void PLIB_USART_IrDAEnable(USART_MODULE_ID index)
void PLIB_PORTS_PinWrite(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, bool value)
void PLIB_USART_HandshakeModeSelect(USART_MODULE_ID index, USART_HANDSHAKE_MODE handshakeConfig)
void PLIB_SPI_BufferWrite16bit(SPI_MODULE_ID index, uint16_t data)
uint16_t PLIB_DMA_ChannelXPeripheralAddressGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_ChannelXCellSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t CellSize)
bool PLIB_DMA_ChannelXNullWriteModeIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_ExistsReceiverAddressDetect(USART_MODULE_ID index)
void SYS_DEBUG_Reinitialize(SYS_MODULE_OBJ object, const SYS_MODULE_INIT *const init)
bool PLIB_PORTS_ExistsSlewRateControl(PORTS_MODULE_ID index)
void PLIB_USART_BaudRateHighEnable(USART_MODULE_ID index)
void DRV_USART0_WriteByte(const uint8_t byte)
DRV_TMR_OPERATION_MODE DRV_TMR3_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
void PLIB_SPI_AudioProtocolEnable(SPI_MODULE_ID index)
void SYS_PORTS_PinPullDownDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_USART_AddressSet(USART_MODULE_ID index, uint8_t address)
void PLIB_USART_LoopbackEnable(USART_MODULE_ID index)
void PLIB_SPI_ClockPolaritySelect(SPI_MODULE_ID index, SPI_CLOCK_POLARITY polarity)
uint8_t DRV_PMP0_Read(void)
void PLIB_USART_IrDADisable(USART_MODULE_ID index)
void DRV_USART_ByteErrorCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
PORTS_DATA_TYPE SYS_PORTS_InterruptStatusGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void Clear_Status(uint8_t bitposn)
bool PLIB_DMA_LastBusAccessIsRead(DMA_MODULE_ID index)
uint32_t PLIB_DMA_RecentAddressAccessed(DMA_MODULE_ID index)
void DRV_TMR_AlarmEnable(DRV_HANDLE handle, bool enable)
void PLIB_USART_TransmitterByteSend(USART_MODULE_ID index, int8_t data)
uint32_t DRV_TMR0_PeriodValueGet(void)
void DRV_USART_Close(const DRV_HANDLE handle)
bool PLIB_DMA_SuspendIsEnabled(DMA_MODULE_ID index)
bool PLIB_PORTS_ExistsPortsDirection(PORTS_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNoticePullUpPerPort(PORTS_MODULE_ID index)
SYS_MODULE_OBJ DRV_USART_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
DRV_TMR_CLIENT_STATUS DRV_TMR3_ClientStatus(void)
void PLIB_PORTS_Write(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value)
DMA_CRC_BYTE_ORDER PLIB_DMA_CRCByteOrderGet(DMA_MODULE_ID index)
void PLIB_USART_RunInSleepModeDisable(USART_MODULE_ID index)
void PLIB_SPI_AudioTransmitModeSelect(SPI_MODULE_ID index, SPI_AUDIO_TRANSMIT_MODE mode)
void PLIB_DMA_ChannelXINTSourceFlagSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
bool PLIB_SPI_ExistsFrameSyncPulseDirection(SPI_MODULE_ID index)
void PLIB_PORTS_ChannelChangeNoticeEdgeEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK edgeRisingMask, PORTS_DATA_MASK edgeFallingMask)
bool PLIB_DMA_ChannelXBusyIsBusy(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_ExistsTransmitterEnable(USART_MODULE_ID index)
bool PLIB_USART_ExistsReceiverOverrunStatus(USART_MODULE_ID index)
SPI_FRAME_PULSE_POLARITY framePulsePolarity
DMA_CHANNEL_ADDRESSING_MODE PLIB_DMA_ChannelXAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_BaudRateAutoDetectIsComplete(USART_MODULE_ID index)
uint32_t DRV_TMR2_CounterValueGet(void)
bool PLIB_DMA_ExistsAbortTransfer(DMA_MODULE_ID index)
void PLIB_USART_BaudRateHighDisable(USART_MODULE_ID index)
DMA_CHANNEL_INT_SOURCE PLIB_DMA_ChannelXTriggerSourceNumberGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_PORTS_Clear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK clearMask)
void SYS_DMA_ChannelAbortEventSet(SYS_DMA_CHANNEL_HANDLE handle, DMA_TRIGGER_SOURCE eventSrc)
bool PLIB_DMA_ExistsChannelXPatternLength(DMA_MODULE_ID index)
void DRV_TMR1_CounterClear(void)
bool PLIB_SPI_TransmitUnderRunStatusGet(SPI_MODULE_ID index)
void PLIB_DMA_CRCAppendModeEnable(DMA_MODULE_ID index)
void PLIB_PORTS_ChannelChangeNoticeDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_PORTS_CnPinsPullUpEnable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
void DRV_TMR3_CounterClear(void)
void PLIB_SPI_AudioProtocolDisable(SPI_MODULE_ID index)
void DRV_TMR3_CounterValueSet(uint32_t value)
uint32_t DRV_TMR1_PeriodValueGet(void)
bool PLIB_DMA_ExistsChannelXPatternIgnore(DMA_MODULE_ID index)
void PLIB_SPI_StopInIdleDisable(SPI_MODULE_ID index)
void DRV_TMR2_Initialize(void)
bool PLIB_PORTS_ExistsPinModePerPort(PORTS_MODULE_ID index)
void PLIB_PORTS_ChannelChangeNoticePullDownEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_SPI_ExistsBusStatus(SPI_MODULE_ID index)
void PLIB_USART_BaudRateAutoDetectEnable(USART_MODULE_ID index)
void PLIB_DMA_ChannelXPatternIgnoreByteDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_DMA_ExistsChannelBits(DMA_MODULE_ID index)
void PLIB_SPI_BaudRateSet(SPI_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
bool PLIB_USART_ExistsReceiverInterruptMode(USART_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXTrigger(DMA_MODULE_ID index)
void PLIB_PORTS_DirectionOutputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
DMA_DESTINATION_ADDRESSING_MODE PLIB_DMA_ChannelXDestinationAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsCommunicationWidth(SPI_MODULE_ID index)
static int qqqstructzzopen
DRV_USART_LINE_CONTROL_SET_RESULT
static unsigned char qqqzzglobflag
bool PLIB_USART_ExistsTransmitter(USART_MODULE_ID index)
void PLIB_PORTS_PinChangeNoticePerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
static void DRV_TMR0_DeInitialize(void)
bool PLIB_SPI_ExistsBaudRateClock(SPI_MODULE_ID index)
void PLIB_USART_TransmitterIdleIsLowDisable(USART_MODULE_ID index)
static void store_switches(void)
SYS_MODULE_OBJ SYS_DEBUG_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
void DRV_USART_TasksError(SYS_MODULE_OBJ object)
void DRV_PMP0_TimingSet(PMP_DATA_WAIT_STATES dataWait, PMP_STROBE_WAIT_STATES strobeWait, PMP_DATA_HOLD_STATES dataHold)
void PLIB_PORTS_DirectionInputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool DRV_SPIn_ReceiverBufferIsFull(void)
void DRV_USART_TasksReceive(SYS_MODULE_OBJ object)
void SYS_DEBUG_Tasks(SYS_MODULE_OBJ object)
bool PLIB_SPI_ExistsReceiveBufferStatus(SPI_MODULE_ID index)
void DRV_ADC_Initialize(void)
DRV_TMR_OPERATION_MODE DRV_TMR_OperationModeGet(DRV_HANDLE handle)
void PLIB_USART_BaudRateSet(USART_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
void PLIB_USART_WakeOnStartDisable(USART_MODULE_ID index)
void PLIB_DMA_StopInIdleDisable(DMA_MODULE_ID index)
void PLIB_PORTS_PinSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_PORTS_PinModePerPortSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_PIN_MODE mode)
bool PLIB_USART_ExistsTransmitterInterruptMode(USART_MODULE_ID index)
bool PLIB_USART_ExistsReceiverAddressAutoDetect(USART_MODULE_ID index)
void SYS_PORTS_ChangeNotificationInIdleModeEnable(PORTS_MODULE_ID index)
void PLIB_USART_ReceiverAddressAutoDetectDisable(USART_MODULE_ID index)
#define DRV_IC_Open(drvIndex, intent)
void DRV_USART_Deinitialize(SYS_MODULE_OBJ object)
DRV_USART_BAUD_SET_RESULT
DRV_HANDLE DRV_IC_Start(const SYS_MODULE_INDEX drvIndex, const DRV_IO_INTENT intent)
struct _DRV_SPI_CLIENT_DATA DRV_SPI_CLIENT_DATA
bool PLIB_DMA_ChannelXAutoIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_ChannelXPatternDataSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t patternData)
void PLIB_DMA_ChannelXChainToLower(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsPinControl(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXDestinationStartAddress(DMA_MODULE_ID index)
bool PLIB_USART_ExistsBaudRateAutoDetect(USART_MODULE_ID index)
static void qqoutput4(FILEPOINT char *s, int i, int j, int k, int l)
static void DRV_TMR2_DeInitialize(void)
uint32_t DRV_TMR4_PeriodValueGet(void)
void PLIB_DMA_ChannelXINTSourceEnable(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
bool PLIB_USART_ExistsTransmitterBufferFullStatus(USART_MODULE_ID index)
void PLIB_SPI_FrameSyncPulseEdgeSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_EDGE edge)
bool PLIB_USART_ReceiverParityErrorHasOccurred(USART_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXEvent(DMA_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNotice(PORTS_MODULE_ID index)
bool SYS_PORTS_PinLatchedGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_PORTS_ExistsChangeNoticePullUp(PORTS_MODULE_ID index)
static SYS_STATUS DRV_TMR2_Status(void)
void PLIB_DMA_ChannelXChainDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_DMA_ChannelXChainIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_ChannelXDestinationStartAddressSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint32_t destinationStartAddress)
SYS_MODULE_OBJ DRV_TMR_Initialize(const SYS_MODULE_INDEX drvIndex, const SYS_MODULE_INIT *const init)
DRV_USART_ERROR DRV_USART_ErrorGet(const DRV_HANDLE client)
bool PLIB_PORTS_ExistsRemapOutput(PORTS_MODULE_ID index)
uint8_t jobQueueReserveSize
void SYS_PORTS_Toggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK toggleMask)
void PLIB_SPI_SlaveSelectEnable(SPI_MODULE_ID index)
void PLIB_USART_ReceiverEnable(USART_MODULE_ID index)
SYS_MODULE_INIT moduleInit
static void DRV_TMR2_Close(void)
bool PLIB_SPI_ExistsBuffer(SPI_MODULE_ID index)
void DRV_SPI_Close(DRV_HANDLE handle)
bool PLIB_USART_TransmitterBreakSendIsComplete(USART_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXAuto(DMA_MODULE_ID index)
void PLIB_PORTS_ChannelChangeNoticePullUpDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool PLIB_USART_ReceiverOverrunHasOccurred(USART_MODULE_ID index)
bool DRV_ADC_SamplesAvailable(uint8_t bufIndex)
size_t DRV_USART_BufferProcessedSizeGet(DRV_USART_BUFFER_HANDLE bufferHandle)
bool PLIB_DMA_ChannelXTriggerIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
DRV_TMR_OPERATION_MODE DRV_TMR_DividerRangeGet(DRV_HANDLE handle, DRV_TMR_DIVIDER_RANGE *pDivRange)
DMA_TRANSFER_MODE PLIB_DMA_ChannelXOperatingTransferModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_USART_StopInIdleDisable(USART_MODULE_ID index)
static void DRV_TMR0_Close(void)
void PLIB_DMA_CRCTypeSet(DMA_MODULE_ID index, DMA_CRC_TYPE CRCType)
static int qqqqbmselwidth
bool PLIB_PORTS_ExistsPinChangeNoticePerPort(PORTS_MODULE_ID index)
static SYS_STATUS DRV_TMR1_Status(void)
void PLIB_DMA_ChannelXPatternLengthSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_PATTERN_LENGTH patternLen)
void * PLIB_USART_ReceiverAddressGet(USART_MODULE_ID index)
bool DRV_TMR_Start(DRV_HANDLE handle)
bool PLIB_DMA_LastBusAccessIsWrite(DMA_MODULE_ID index)
static int qqqisinitialised
void PLIB_SPI_BufferClear(SPI_MODULE_ID index)
void SYS_DMA_ChannelTransferAdd(SYS_DMA_CHANNEL_HANDLE handle, const void *srcAddr, size_t srcSize, const void *destAddr, size_t destSize, size_t cellSize)
void PLIB_DMA_ChannelXChainEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
PORTS_DATA_TYPE PLIB_PORTS_Read(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_SPI_ExistsMasterControl(SPI_MODULE_ID index)
bool PLIB_PORTS_PinGetLatched(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_DMA_ChannelXSourceAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_SOURCE_ADDRESSING_MODE sourceAddressMode)
void PLIB_SPI_BufferWrite(SPI_MODULE_ID index, uint8_t data)
void PLIB_DMA_Disable(DMA_MODULE_ID index)
bool PLIB_DMA_ChannelXReloadIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_StartTransferSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void Prepare_Return_B(uint8_t byt [])
void SYS_PORTS_ChangeNotificationGlobalEnable(PORTS_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXPatternIgnoreByte(DMA_MODULE_ID index)
uint32_t DRV_TMR3_CounterFrequencyGet(void)
bool PLIB_DMA_IsBusy(DMA_MODULE_ID index)
bool PLIB_SPI_ExistsEnableControl(SPI_MODULE_ID index)
void SYS_DMA_Resume(void)
bool PLIB_SPI_ExistsFIFOInterruptMode(SPI_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNoticePerPortInIdle(PORTS_MODULE_ID index)
void PLIB_USART_Transmitter9BitsSend(USART_MODULE_ID index, int8_t data, bool Bit9th)
DMA_CHANNEL_DATA_SIZE PLIB_DMA_ChannelXDataSizeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint8_t over_current_count
bool PLIB_DMA_ChannelXEventIsDetected(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint16_t PLIB_SPI_BufferRead16bit(SPI_MODULE_ID index)
bool PLIB_DMA_ChannelXINTSourceIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
void SYS_PORTS_PinSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
INT_SOURCE txInterruptSource
bool PLIB_PORTS_ExistsChannelChangeNoticeMethod(PORTS_MODULE_ID index)
bool PLIB_SPI_Exists32bitBuffer(SPI_MODULE_ID index)
void PLIB_USART_TransmitterInterruptModeSelect(USART_MODULE_ID index, USART_TRANSMIT_INTR_MODE fifolevel)
static void execute_switches(void)
bool PLIB_SPI_ExistsTransmitBufferEmptyStatus(SPI_MODULE_ID index)
void SYS_PORTS_Set(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value, PORTS_DATA_MASK mask)
void * PLIB_USART_TransmitterAddressGet(USART_MODULE_ID index)
uint16_t PLIB_DMA_ChannelXPatternDataGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
DRV_USART_BUFFER_RESULT DRV_USART_BufferRemove(DRV_USART_BUFFER_HANDLE bufferHandle)
bool PLIB_USART_ExistsTransmitter9BitsSend(USART_MODULE_ID index)
void PLIB_SPI_ReceiverOverflowClear(SPI_MODULE_ID index)
void DRV_TMR3_Initialize(void)
bool PLIB_PORTS_ExistsChangeNoticeEdgeStatus(PORTS_MODULE_ID index)
DRV_USART_TRANSFER_STATUS
bool PLIB_USART_ExistsTransmitterBreak(USART_MODULE_ID index)
void DRV_PMP0_Write(uint8_t data)
bool PLIB_DMA_ExistsCRCAppendMode(DMA_MODULE_ID index)
void PLIB_DMA_CRCXOREnableSet(DMA_MODULE_ID index, uint32_t DMACRCXOREnableMask)
SYS_DMA_CHANNEL_IGNORE_MATCH
bool PLIB_DMA_ChannelXBufferedDataIsWritten(DMA_MODULE_ID index, DMA_CHANNEL channel)
SPI_FRAME_PULSE_DIRECTION framePulseDirection
void PLIB_PORTS_ChannelChangeNoticeEdgeDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK edgeRisingMask, PORTS_DATA_MASK edgeFallingMask)
void PLIB_SPI_PinEnable(SPI_MODULE_ID index, SPI_PIN pin)
SYS_ERROR_LEVEL gblErrLvl
void DRV_ADC0_Close(void)
unsigned int DRV_USART_ReceiverBufferSizeGet(const DRV_HANDLE handle)
static struct bitmapstruct_t bitmapstruct
void SYS_DMA_Tasks(SYS_MODULE_OBJ object, DMA_CHANNEL activeChannel)
TMR_PRESCALE DRV_TMR4_PrescalerGet(void)
bool PLIB_DMA_ExistsLastBusAccess(DMA_MODULE_ID index)
void DRV_USART_BufferAddRead(const DRV_HANDLE handle, DRV_USART_BUFFER_HANDLE *const bufferHandle, void *buffer, const size_t size)
void PLIB_DMA_ChannelXTriggerDisable(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
void PLIB_DMA_ChannelXTransferCountSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t transferCount)
void DRV_TMR0_StopInIdleEnable(void)
void DRV_TMR4_StopInIdleDisable(void)
bool PLIB_DMA_ExistsCRCXOREnable(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsCRCPolynomialLength(DMA_MODULE_ID index)
void PLIB_SPI_SlaveEnable(SPI_MODULE_ID index)
void SYS_DMA_ChannelForceStart(SYS_DMA_CHANNEL_HANDLE handle)
bool PLIB_DMA_ExistsChannelX(DMA_MODULE_ID index)
DRV_USART_BAUD_SET_RESULT DRV_USART_BaudSet(const DRV_HANDLE client, uint32_t baud)
bool PLIB_USART_ExistsOperationMode(USART_MODULE_ID index)
void DRV_USART_ByteTransmitCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
bool PLIB_DMA_ExistsRecentAddress(DMA_MODULE_ID index)
bool DRV_TMR_GateModeClear(DRV_HANDLE handle)
uint16_t PLIB_DMA_ChannelXDestinationPointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
PORTS_CHANGE_NOTICE_METHOD PLIB_PORTS_ChannelChangeNoticeMethodGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
PORTS_DATA_TYPE SYS_PORTS_LatchedGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_PORTS_ChangeNoticeInIdleEnable(PORTS_MODULE_ID index)
DRV_SPI_PROTOCOL_TYPE spiProtocolType
void PLIB_DMA_ChannelXOperatingTransferModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRANSFER_MODE channeltransferMode)
uint32_t DRV_TMR3_PeriodValueGet(void)
bool DRV_USART0_ReceiverBufferIsEmpty(void)
SPI_FRAME_PULSE_WIDTH framePulseWidth
uint32_t DRV_TMR_AlarmPeriodGet(DRV_HANDLE handle)
void PLIB_PORTS_CnPinsEnable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
void PLIB_SPI_FramedCommunicationEnable(SPI_MODULE_ID index)
uint16_t DRV_IC_Capture16BitDataRead(DRV_HANDLE handle)
uint8_t PLIB_DMA_ChannelXPatternIgnoreGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void(* DRV_USART_BYTE_EVENT_HANDLER)(const SYS_MODULE_INDEX index)
void PLIB_DMA_ChannelXReloadDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool SYS_PORTS_PinRead(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_PORTS_PinChangeNoticeEdgeIsEnabled(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_CHANGE_NOTICE_EDGE cnEdgeType)
void PLIB_USART_InitializeOperation(USART_MODULE_ID index, USART_RECEIVE_INTR_MODE receiveInterruptMode, USART_TRANSMIT_INTR_MODE transmitInterruptMode, USART_OPERATION_MODE operationMode)
bool PLIB_USART_TransmitterBufferIsFull(USART_MODULE_ID index)
bool PLIB_SPI_ExistsFIFOShiftRegisterEmptyStatus(SPI_MODULE_ID index)
bool PLIB_DMA_ChannelXPatternIgnoreByteIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_ChannelXChainToHigher(DMA_MODULE_ID index, DMA_CHANNEL channel)
static void read_switches(void)
void PLIB_USART_ReceiverInterruptModeSelect(USART_MODULE_ID index, USART_RECEIVE_INTR_MODE interruptMode)
void SYS_PORTS_ChangeNotificationEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum, SYS_PORTS_PULLUP_PULLDOWN_STATUS value)
bool SYS_DMA_ChannelIsBusy(SYS_DMA_CHANNEL_HANDLE handle)
DMA_CHANNEL_PRIORITY PLIB_DMA_ChannelXPriorityGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_DMA_IsEnabled(DMA_MODULE_ID index)
void DRV_TMR1_Initialize(void)
bool PLIB_USART_ExistsReceiver9Bits(USART_MODULE_ID index)
void PLIB_PORTS_ChannelChangeNoticeEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_DMA_SuspendDisable(DMA_MODULE_ID index)
void PLIB_PORTS_AnPinsModeSelect(PORTS_MODULE_ID index, PORTS_AN_PIN anPins, PORTS_PIN_MODE mode)
bool PLIB_SPI_FIFOShiftRegisterIsEmpty(SPI_MODULE_ID index)
void PLIB_PORTS_ChangeNoticePullUpPerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
SYS_MODULE_OBJ DRV_USART0_Initialize(void)
TMR_PRESCALE DRV_TMR3_PrescalerGet(void)
void SYS_DMA_ChannelSetup(SYS_DMA_CHANNEL_HANDLE handle, SYS_DMA_CHANNEL_OP_MODE modeEnable, DMA_TRIGGER_SOURCE eventSrc)
void PLIB_USART_BaudRateHighSet(USART_MODULE_ID index, uint32_t clockFrequency, uint32_t baudRate)
void PLIB_SPI_ErrorInterruptEnable(SPI_MODULE_ID index, SPI_ERROR_INTERRUPT error)
void PLIB_PORTS_PinModeSelect(PORTS_MODULE_ID index, PORTS_ANALOG_PIN pin, PORTS_PIN_MODE mode)
bool PLIB_USART_ReceiverDataIsAvailable(USART_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXINTSourceFlag(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXBusy(DMA_MODULE_ID index)
static DRV_TMR_OPERATION_MODE DRV_TMR3_OperationModeGet(void)
void(* SYS_DMA_CHANNEL_TRANSFER_EVENT_HANDLER)(SYS_DMA_TRANSFER_EVENT event, SYS_DMA_CHANNEL_HANDLE handle, uintptr_t contextHandle)
void PLIB_PORTS_PinOpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_PORTS_RemapInput(PORTS_MODULE_ID index, PORTS_REMAP_INPUT_FUNCTION inputFunction, PORTS_REMAP_INPUT_PIN remapInputPin)
void SYS_PORTS_ChangeNotificationInIdleModeDisable(PORTS_MODULE_ID index)
bool PLIB_DMA_ChannelXIsEnabled(DMA_MODULE_ID index, DMA_CHANNEL channel)
static void DRV_TMR4_DeInitialize(void)
bool PLIB_SPI_ExistsTransmitBufferFullStatus(SPI_MODULE_ID index)
DMA_PATTERN_LENGTH PLIB_DMA_ChannelXPatternLengthGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
TMR_PRESCALE DRV_TMR0_PrescalerGet(void)
bool PLIB_USART_ExistsReceiverAddressMask(USART_MODULE_ID index)
bool PLIB_USART_ExistsBaudRateHigh(USART_MODULE_ID index)
uint32_t DRV_TMR_CounterFrequencyGet(DRV_HANDLE handle)
bool PLIB_PORTS_ExistsLatchRead(PORTS_MODULE_ID index)
bool PLIB_SPI_ExistsFrameSyncPulseCounter(SPI_MODULE_ID index)
void SYS_PORTS_PinToggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
DRV_HANDLE DRV_USART0_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT ioIntent)
bool PLIB_SPI_ExistsFrameSyncPulseWidth(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsChannelXChainEnbl(DMA_MODULE_ID index)
void PLIB_PORTS_ChannelChangeNoticePullUpEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
uint32_t DRV_TMR3_CounterValueGet(void)
bool PLIB_SPI_ReadDataIsSignExtended(SPI_MODULE_ID index)
bool PLIB_DMA_ExistsCRCByteOrder(DMA_MODULE_ID index)
SYS_PORTS_PULLUP_PULLDOWN_STATUS
DMA_CHANNEL_TRANSFER_DIRECTION PLIB_DMA_ChannelXTransferDirectionGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void SYS_PORTS_RemapOutput(PORTS_MODULE_ID index, PORTS_REMAP_OUTPUT_FUNCTION function, PORTS_REMAP_OUTPUT_PIN remapPin)
bool PLIB_DMA_ExistsCRCChannel(DMA_MODULE_ID index)
uint32_t PLIB_USART_BaudRateGet(USART_MODULE_ID index, int32_t clockFrequency)
uint16_t PLIB_DMA_ChannelXCellSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
DRV_USART_TRANSFER_STATUS DRV_USART0_TransferStatus(void)
void PLIB_DMA_ChannelXEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_PORTS_OpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
DMA_SOURCE_ADDRESSING_MODE PLIB_DMA_ChannelXSourceAddressModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_PORTS_ChangeNoticePullDownPerPortEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_USART_TransmitterIdleIsLowEnable(USART_MODULE_ID index)
void PLIB_USART_OperationModeSelect(USART_MODULE_ID index, USART_OPERATION_MODE operationmode)
bool PLIB_PORTS_PinGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_SPI_ExistsFramedCommunication(SPI_MODULE_ID index)
TMR_PRESCALE DRV_TMR_PrescalerGet(DRV_HANDLE handle)
struct _DRV_SPI_INIT DRV_SPI_INIT
void SYS_DMA_ChannelRelease(SYS_DMA_CHANNEL_HANDLE handle)
void PLIB_PORTS_ChangeNoticePerPortTurnOn(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
DRV_SPI_BUFFER_TYPE bufferType
DRV_TMR_OPERATION_MODE DRV_TMR1_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
void PLIB_USART_Enable(USART_MODULE_ID index)
void SYS_PORTS_RemapInput(PORTS_MODULE_ID index, PORTS_REMAP_INPUT_FUNCTION function, PORTS_REMAP_INPUT_PIN remapPin)
void SYS_PORTS_OpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
void PLIB_DMA_ChannelXTriggerEnable(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRIGGER_TYPE trigger)
bool DRV_USART_TransmitBufferIsFull(const DRV_HANDLE handle)
bool PLIB_DMA_ExistsSuspend(DMA_MODULE_ID index)
bool PLIB_USART_ExistsReceiverFramingErrorStatus(USART_MODULE_ID index)
void DRV_USART0_Deinitialize(void)
uint32_t PLIB_DMA_CRCDataRead(DMA_MODULE_ID index)
void PLIB_PORTS_ChangeNoticeInIdleDisable(PORTS_MODULE_ID index)
void PLIB_SPI_FIFODisable(SPI_MODULE_ID index)
bool PLIB_USART_TransmitterIsEmpty(USART_MODULE_ID index)
void PLIB_PORTS_PinChangeNoticeEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
static void DRV_TMR4_Open(void)
bool PLIB_USART_ReceiverFramingErrorHasOccurred(USART_MODULE_ID index)
uint32_t DRV_TMR4_CounterValueGet(void)
void PLIB_PORTS_PinChangeNoticeDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
DRV_SPI_BUFFER_EVENT DRV_SPI_BufferStatus(DRV_SPI_BUFFER_HANDLE bufferHandle)
void DRV_TMR_Stop(DRV_HANDLE handle)
size_t SYS_DMA_ChannelDestinationTransferredSizeGet(SYS_DMA_CHANNEL_HANDLE handle)
void DRV_ADC1_Close(void)
DRV_USART_TRANSFER_STATUS
bool PLIB_DMA_ChannelXCollisionStatus(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_COLLISION collisonType)
void PLIB_PORTS_ChangeNoticePerPortTurnOff(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
SYS_ERROR_LEVEL SYS_DEBUG_ErrorLevelGet(void)
void DRV_USART_WriteByte(const DRV_HANDLE handle, const uint8_t byte)
DRV_USART_ERROR DRV_USART0_ErrorGet(void)
void PLIB_DMA_CRCAppendModeDisable(DMA_MODULE_ID index)
void PLIB_USART_RunInOverflowDisable(USART_MODULE_ID index)
static void DRV_TMR0_Open(void)
void PLIB_DMA_ChannelXDataSizeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_DATA_SIZE channelDataSize)
void PLIB_DMA_ChannelXDisabledDisablesEvents(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsFrameSyncPulsePolarity(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_ADDRESSING_MODE channelAddressMode)
static int wl_sps_50zqendz(int qqqi)
DMA_CRC_TYPE PLIB_DMA_CRCTypeGet(DMA_MODULE_ID index)
bool PLIB_USART_ExistsBRGClockSourceSelect(USART_MODULE_ID index)
static int wl_sps_50zqzqzq(int qqqi)
void PLIB_USART_ReceiverAddressDetectEnable(USART_MODULE_ID index)
uint8_t DRV_USART0_ReadByte(void)
DRV_SPI_BUFFER_EVENT_HANDLER operationStarting
void PLIB_SPI_CommunicationWidthSelect(SPI_MODULE_ID index, SPI_COMMUNICATION_WIDTH width)
bool PLIB_USART_ExistsTransmitterIdleIsLow(USART_MODULE_ID index)
void SYS_PORTS_ChangeNotificationDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
DRV_HANDLE DRV_SPI_Open(const SYS_MODULE_INDEX drvIndex, const DRV_IO_INTENT ioIntent)
bool PLIB_DMA_ExistsChannelXPriority(DMA_MODULE_ID index)
void PLIB_SPI_FrameErrorStatusClear(SPI_MODULE_ID index)
uint8_t DRV_USART_ReadByte(const DRV_HANDLE handle)
void PLIB_DMA_ChannelXSourceStartAddressSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint32_t sourceStartAddress)
static void DRV_TMR0_Tasks(void)
void SYS_PORTS_PinClear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_SPI_FrameSyncPulseDirectionSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_DIRECTION direction)
SYS_DMA_CHANNEL_IGNORE_MATCH
DRV_TMR_CLIENT_STATUS DRV_TMR1_ClientStatus(void)
void PLIB_SPI_InputSamplePhaseSelect(SPI_MODULE_ID index, SPI_INPUT_SAMPLING_PHASE phase)
void SYS_PORTS_DirectionSelect(PORTS_MODULE_ID index, SYS_PORTS_PIN_DIRECTION pinDir, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddRead2(DRV_HANDLE handle, void *rxBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
void PLIB_DMA_StopInIdleEnable(DMA_MODULE_ID index)
void DRV_IC0_Initialize(void)
DRV_TMR_CLIENT_STATUS DRV_TMR2_ClientStatus(void)
bool PLIB_USART_ExistsReceiverIdleStateLowEnable(USART_MODULE_ID index)
void DRV_TMR_AlarmDeregister(DRV_HANDLE handle)
void SYS_PORTS_PinWrite(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, bool value)
static void DRV_TMR4_Tasks(void)
void PLIB_USART_ReceiverDisable(USART_MODULE_ID index)
void SYS_DEBUG_Deinitialize(SYS_MODULE_OBJ object)
bool PLIB_SPI_ReceiverFIFOIsEmpty(SPI_MODULE_ID index)
void qqqtotalupload(void)
bool DRV_TMR_GateModeSet(DRV_HANDLE handle)
bool PLIB_PORTS_ExistsAnPinsMode(PORTS_MODULE_ID index)
void SYS_PORTS_PinPullUpEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_DMA_ExistsCRCType(DMA_MODULE_ID index)
bool PLIB_USART_ExistsReceiverAddress(USART_MODULE_ID index)
SPI_FRAME_PULSE_EDGE framePulseEdge
void PLIB_USART_AddressMaskSet(USART_MODULE_ID index, uint8_t mask)
static int wl_sps_50zqqzqz(qqnull_params)
bool PLIB_SPI_ExistsStopInIdleControl(SPI_MODULE_ID index)
uintptr_t DRV_USART_BUFFER_HANDLE
DRV_USART_LINE_CONTROL_SET_RESULT DRV_USART0_LineControlSet(DRV_USART_LINE_CONTROL lineControlMode)
static void qqqupload(qqnull_params)
void PLIB_SPI_PinDisable(SPI_MODULE_ID index, SPI_PIN pin)
void PLIB_DMA_ChannelXDestinationSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t destinationSize)
bool DRV_USART0_TransmitBufferIsFull(void)
void PLIB_USART_InitializeModeGeneral(USART_MODULE_ID index, bool autobaud, bool loopBackMode, bool wakeFromSleep, bool irdaMode, bool stopInIdle)
void PLIB_SPI_FrameSyncPulsePolaritySelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_POLARITY polarity)
void PLIB_SPI_StopInIdleEnable(SPI_MODULE_ID index)
void SYS_PORTS_PinOpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_DMA_ExistsChannelXChain(DMA_MODULE_ID index)
void PLIB_SPI_ErrorInterruptDisable(SPI_MODULE_ID index, SPI_ERROR_INTERRUPT error)
bool PLIB_PORTS_PinChangeNoticeEdgeHasOccurred(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
DRV_TMR_OPERATION_MODE DRV_TMR4_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
bool DRV_TMR3_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
static void DRV_TMR1_Tasks(void)
bool PLIB_DMA_CRCAppendModeIsEnabled(DMA_MODULE_ID index)
void Set_Status(uint8_t bitposn)
void SYS_DEBUG_Print(const char *format,...)
bool PLIB_PORTS_ExistsPortsWrite(PORTS_MODULE_ID index)
SYS_STATUS SYS_DEBUG_Status(SYS_MODULE_OBJ object)
static void qqoutput3(FILEPOINT char *s, int i, int j, int k)
uint32_t PLIB_DMA_ChannelXDestinationStartAddressGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
bool PLIB_DMA_ExistsChannelXCellProgressPointer(DMA_MODULE_ID index)
uintptr_t DRV_USART_BUFFER_HANDLE
static DRV_TMR_OPERATION_MODE DRV_TMR1_OperationModeGet(void)
void PLIB_DMA_ChannelXINTSourceFlagClear(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
void DRV_TMR4_CounterClear(void)
bool DRV_TMR4_Start(void)
bool PLIB_USART_ExistsRunInOverflow(USART_MODULE_ID index)
void(* DRV_SPI_BUFFER_EVENT_HANDLER)(DRV_SPI_BUFFER_EVENT event, DRV_SPI_BUFFER_HANDLE bufferHandle, void *context)
bool PLIB_USART_ExistsIrDA(USART_MODULE_ID index)
bool PLIB_USART_ExistsReceiverParityErrorStatus(USART_MODULE_ID index)
void PLIB_USART_ReceiverOverrunErrorClear(USART_MODULE_ID index)
int16_t PLIB_USART_Receiver9BitsReceive(USART_MODULE_ID index)
USART_ERROR PLIB_USART_ErrorsGet(USART_MODULE_ID index)
void SYS_PORTS_PinPullDownEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void SYS_PORTS_PinPullUpDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void PLIB_SPI_TransmitUnderRunStatusClear(SPI_MODULE_ID index)
bool PLIB_USART_ExistsReceiverIdleStatus(USART_MODULE_ID index)
SYS_MODULE_OBJ DRV_IC_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
void SYS_DMA_ChannelTransferSet(SYS_DMA_CHANNEL_HANDLE handle, const void *srcAddr, size_t srcSize, const void *destAddr, size_t destSize, size_t cellSize)
PORTS_PIN_SLEW_RATE PLIB_PORTS_PinSlewRateGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_DMA_ExistsCRC(DMA_MODULE_ID index)
uint32_t DRV_TMR0_CounterFrequencyGet(void)
void Prepare_Return_A(uint8_t byte, uint16_t data2, uint16_t data1)
bool PLIB_PORTS_ExistsChangeNoticeInIdle(PORTS_MODULE_ID index)
bool PLIB_PORTS_ExistsPortsRead(PORTS_MODULE_ID index)
DRV_SPI_BUFFER_EVENT_HANDLER operationEnded
static void process_switches(void)
bool PLIB_PORTS_ExistsChangeNoticeEdgeControl(PORTS_MODULE_ID index)
bool PLIB_SPI_FrameErrorStatusGet(SPI_MODULE_ID index)
void PLIB_PORTS_ChannelChangeNoticeMethodSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_CHANGE_NOTICE_METHOD changeNoticeMethod)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWriteRead(DRV_HANDLE handle, void *txBuffer, size_t txSize, void *rxBuffer, size_t rxSize, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
CLK_BUSES_PERIPHERAL spiClk
bool PLIB_USART_WakeOnStartIsEnabled(USART_MODULE_ID index)
static SYS_STATUS DRV_TMR0_Status(void)
void SYS_DMA_ChannelResume(SYS_DMA_CHANNEL_HANDLE handle)
void PLIB_DMA_ChannelXAutoDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void DRV_USART_TasksTransmit(SYS_MODULE_OBJ object)
void SYS_DMA_ChannelSuspend(SYS_DMA_CHANNEL_HANDLE handle)
bool PLIB_USART_ExistsWakeOnStart(USART_MODULE_ID index)
void PLIB_DMA_CRCPolynomialLengthSet(DMA_MODULE_ID index, uint8_t polyLength)
void PLIB_DMA_AbortTransferSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
uint32_t DRV_TMR2_PeriodValueGet(void)
void PLIB_DMA_Enable(DMA_MODULE_ID index)
void Set_WL_SPS_CurrentLimit(uint16_t value)
DRV_USART_LINE_CONTROL_SET_RESULT
void PLIB_USART_BRGClockSourceSelect(USART_MODULE_ID index, USART_BRG_CLOCK_SOURCE brgClockSource)
bool PLIB_USART_ExistsLineControlMode(USART_MODULE_ID index)
bool DRV_TMR1_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
bool PLIB_DMA_ExistsChannelXSourceSize(DMA_MODULE_ID index)
void SYS_PORTS_PinOpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void SYS_PORTS_ChangeNotificationGlobalDisable(PORTS_MODULE_ID index)
bool DRV_TMR0_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
SPI_COMMUNICATION_WIDTH commWidth
void DRV_TMR0_CounterClear(void)
uint32_t PLIB_DMA_CRCXOREnableGet(DMA_MODULE_ID index)
void PLIB_PORTS_ChangeNoticeEnable(PORTS_MODULE_ID index)
void PLIB_PORTS_ChangeNoticePullUpEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
size_t SYS_DMA_ChannelSourceTransferredSizeGet(SYS_DMA_CHANNEL_HANDLE handle)
bool PLIB_SPI_ExistsInputSamplePhase(SPI_MODULE_ID index)
DRV_HANDLE DRV_TMR_Open(const SYS_MODULE_INDEX index, const DRV_IO_INTENT intent)
bool PLIB_SPI_ReceiverHasOverflowed(SPI_MODULE_ID index)
void PLIB_DMA_CRCWriteByteOrderAlter(DMA_MODULE_ID index)
bool PLIB_USART_ExistsHandshakeMode(USART_MODULE_ID index)
bool DRV_SPIn_TransmitterBufferIsFull(void)
void PLIB_DMA_ChannelXAutoEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_PORTS_PinOpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_DMA_ExistsChannelXStartIRQ(DMA_MODULE_ID index)
void DRV_USART0_TasksError(void)
void PLIB_SPI_MasterEnable(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXStartIRQSet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRIGGER_SOURCE IRQnum)
void SYS_DMA_TasksError(SYS_MODULE_OBJ object)
void PLIB_PORTS_ChangeNoticePullUpDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
bool PLIB_USART_RunInOverflowIsEnabled(USART_MODULE_ID index)
static DRV_TMR_OPERATION_MODE DRV_TMR4_OperationModeGet(void)
uint16_t upper_current_limit
void PLIB_USART_TransmitterEnable(USART_MODULE_ID index)
void PLIB_PORTS_ChannelChangeNoticePullDownDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
ldra_void_function qqqaccumupload[QQQnumfil]
static SYS_STATUS DRV_TMR3_Status(void)
void PLIB_SPI_AudioCommunicationWidthSelect(SPI_MODULE_ID index, SPI_AUDIO_COMMUNICATION_WIDTH mode)
uint16_t upper_voltage_limit
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWriteRead2(DRV_HANDLE handle, void *txBuffer, size_t txSize, void *rxBuffer, size_t rxSize, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
void PLIB_DMA_ChannelXTransferDirectionSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_TRANSFER_DIRECTION chTransferDirection)
uint32_t DRV_IC_Capture32BitDataRead(DRV_HANDLE handle)
void DRV_USART0_TasksReceive(void)
SYS_DMA_ERROR SYS_DMA_ChannelErrorGet(SYS_DMA_CHANNEL_HANDLE handle)
bool PLIB_SPI_ExistsClockPolarity(SPI_MODULE_ID index)
void PLIB_SPI_AudioErrorDisable(SPI_MODULE_ID index, SPI_AUDIO_ERROR error)
SYS_PORTS_PULLUP_PULLDOWN_STATUS
bool PLIB_SPI_ExistsFIFOCount(SPI_MODULE_ID index)
void DRV_TMR1_CounterValueSet(uint32_t value)
SYS_STATUS DRV_TMR_Status(SYS_MODULE_OBJ object)
void PLIB_DMA_ChannelXDisabledEnablesEvents(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_USART_WakeOnStartEnable(USART_MODULE_ID index)
size_t DRV_USART_BufferCompletedBytesGet(DRV_USART_BUFFER_HANDLE bufferHandle)
void DRV_ADC_DeInitialize(void)
void PLIB_DMA_CRCBitOrderSelect(DMA_MODULE_ID index, DMA_CRC_BIT_ORDER bitOrder)
void SYS_PORTS_Initialize()
uint32_t PLIB_SPI_BufferRead32bit(SPI_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNoticePerPortTurnOn(PORTS_MODULE_ID index)
void PLIB_DMA_CRCDisable(DMA_MODULE_ID index)
void SYS_PORTS_InterruptEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos, PORTS_PIN_INTERRUPT_TYPE pinInterruptType)
bool PLIB_PORTS_ExistsPinMode(PORTS_MODULE_ID index)
DRV_TMR_CLIENT_STATUS DRV_TMR_ClientStatus(DRV_HANDLE handle)
DRV_SPI_BUFFER_EVENT_HANDLER operationEnded
bool PLIB_SPI_ExistsErrorInterruptControl(SPI_MODULE_ID index)
static void qqqbitmapreset(qqnull_params)
void DRV_USART_ByteReceiveCallbackSet(const SYS_MODULE_INDEX index, const DRV_USART_BYTE_EVENT_HANDLER eventHandler)
void PLIB_DMA_BusyActiveSet(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsEnableControl(DMA_MODULE_ID index)
bool PLIB_USART_ExistsRunInSleepMode(USART_MODULE_ID index)
uintptr_t DRV_SPI_BUFFER_HANDLE
uint8_t PLIB_USART_AddressGet(USART_MODULE_ID index)
bool PLIB_USART_ExistsLoopback(USART_MODULE_ID index)
void PLIB_DMA_ChannelXStartAddressOffsetSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t address, DMA_ADDRESS_OFFSET_TYPE offset)
uint32_t PLIB_DMA_ChannelXSourceStartAddressGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void PLIB_DMA_ChannelXNullWriteModeDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
void PLIB_DMA_ChannelPrioritySelect(DMA_MODULE_ID index, DMA_CHANNEL_PRIORITY channelPriority)
static DRV_TMR_OPERATION_MODE DRV_TMR2_OperationModeGet(void)
void DRV_TMR_Close(DRV_HANDLE handle)
static SYS_STATUS DRV_TMR4_Status(void)
bool PLIB_SPI_ExistsBaudRate(SPI_MODULE_ID index)
static void qqoutput2(FILEPOINT char *s, int i, int j)
void(* DRV_USART_BUFFER_EVENT_HANDLER)(DRV_USART_BUFFER_EVENT event, DRV_USART_BUFFER_HANDLE bufferHandle, uintptr_t context)
void PLIB_SPI_FIFOInterruptModeSelect(SPI_MODULE_ID index, SPI_FIFO_INTERRUPT mode)
void PLIB_PORTS_PinClear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
uint32_t DRV_IC0_Capture32BitDataRead(void)
void(* ldra_void_function)()
bool PLIB_DMA_ExistsChannelXPatternData(DMA_MODULE_ID index)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWrite(DRV_HANDLE handle, void *txBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
void DRV_IC_Stop(DRV_HANDLE handle)
void PLIB_PORTS_OpenDrainEnable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddWrite2(DRV_HANDLE handle, void *txBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context, DRV_SPI_BUFFER_HANDLE *jobHandle)
void PLIB_DMA_CRCEnable(DMA_MODULE_ID index)
static void DRV_TMR3_DeInitialize(void)
void PLIB_PORTS_Set(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value, PORTS_DATA_MASK mask)
void DRV_TMR3_StopInIdleDisable(void)
void PLIB_USART_TransmitterDisable(USART_MODULE_ID index)
void PLIB_DMA_ChannelXSourceSizeSet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, uint16_t sourceSize)
USART_BRG_CLOCK_SOURCE PLIB_USART_BRGClockSourceGet(USART_MODULE_ID index)
uint32_t DRV_TMR4_CounterFrequencyGet(void)
uint8_t PLIB_SPI_BufferRead(SPI_MODULE_ID index)
void SYS_DMA_ChannelDisable(SYS_DMA_CHANNEL_HANDLE handle)
void SYS_PORTS_Clear(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK clearMask)
void PLIB_DMA_ChannelXNullWriteModeEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
uintptr_t SYS_DMA_CHANNEL_HANDLE
bool PLIB_DMA_ExistsChannelXINTSource(DMA_MODULE_ID index)
DRV_TMR_OPERATION_MODE DRV_TMR0_DividerRangeGet(DRV_TMR_DIVIDER_RANGE *pDivRange)
static DRV_TMR_OPERATION_MODE DRV_TMR0_OperationModeGet(void)
void PLIB_USART_BaudSetAndEnable(USART_MODULE_ID index, uint32_t systemClock, uint32_t baud)
DRV_USART_TRANSFER_STATUS DRV_USART_TransferStatus(const DRV_HANDLE handle)
bool SYS_DMA_IsBusy(void)
bool new_current_values_flag
void PLIB_SPI_BufferWrite32bit(SPI_MODULE_ID index, uint32_t data)
void SYS_PORTS_ChangeNotificationPullUpDisable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
uint16_t PLIB_DMA_ChannelXDestinationSizeGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
void PLIB_SPI_AudioErrorEnable(SPI_MODULE_ID index, SPI_AUDIO_ERROR error)
void SYS_PORTS_PinModeSelect(PORTS_MODULE_ID index, PORTS_ANALOG_PIN pin, PORTS_PIN_MODE mode)
uint32_t DRV_TMR_CounterValueGet(DRV_HANDLE handle)
void DRV_TMR0_PeriodValueSet(uint32_t value)
bool new_voltage_values_flag
SPI_INPUT_SAMPLING_PHASE inputSamplePhase
SYS_DMA_CHANNEL_HANDLE SYS_DMA_ChannelAllocate(DMA_CHANNEL channel)
bool PLIB_SPI_ExistsAudioTransmitMode(SPI_MODULE_ID index)
DRV_SPI_BUFFER_EVENT_HANDLER operationStarting
void DRV_PMP0_ModeConfig(void)
bool PLIB_SPI_ExistsOutputDataPhase(SPI_MODULE_ID index)
void PLIB_DMA_ChannelXDestinationAddressModeSelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_DESTINATION_ADDRESSING_MODE destinationAddressMode)
DRV_SPI_BUFFER_HANDLE DRV_SPI_BufferAddRead(DRV_HANDLE handle, void *rxBuffer, size_t size, DRV_SPI_BUFFER_EVENT_HANDLER completeCB, void *context)
void DRV_TMR2_StopInIdleEnable(void)
void SYS_PORTS_Write(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_TYPE value)
unsigned int DRV_USART0_ReceiverBufferSizeGet(void)
void DRV_TMR_AlarmPeriodSet(DRV_HANDLE handle, uint32_t value)
static void DRV_TMR1_Open(void)
static void DRV_TMR3_Open(void)
void(* DRV_TMR_CALLBACK)(uintptr_t context, uint32_t alarmCount)
uint16_t PLIB_DMA_ChannelXStartAddressOffsetGet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_ADDRESS_OFFSET_TYPE offset)
void DRV_TMR0_StopInIdleDisable(void)
void PLIB_SPI_AudioProtocolModeSelect(SPI_MODULE_ID index, SPI_AUDIO_PROTOCOL mode)
DRV_USART_CLIENT_STATUS DRV_USART0_ClientStatus(void)
size_t DRV_USART_Write(const DRV_HANDLE handle, void *buffer, const size_t numbytes)
void DRV_SPI_Deinitialize(SYS_MODULE_OBJ object)
void SYS_PORTS_ChangeNotificationPullUpEnable(PORTS_MODULE_ID index, PORTS_CHANGE_NOTICE_PIN pinNum)
bool PLIB_PORTS_ExistsChangeNoticePullDownPerPort(PORTS_MODULE_ID index)
uint8_t overvoltage_count
bool DRV_TMR4_ClockSet(DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE prescale)
bool PLIB_USART_ExistsTransmitterEmptyStatus(USART_MODULE_ID index)
void PLIB_PORTS_Toggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK toggleMask)
bool PLIB_SPI_ReceiverBufferIsFull(SPI_MODULE_ID index)
static void DRV_TMR1_DeInitialize(void)
void SYS_PORTS_OpenDrainDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK mask)
bool DRV_TMR_AlarmDisable(DRV_HANDLE handle)
void DRV_TMR4_StopInIdleEnable(void)
void * PLIB_SPI_BufferAddressGet(SPI_MODULE_ID index)
bool PLIB_PORTS_ExistsPinChangeNotice(PORTS_MODULE_ID index)
uint16_t PLIB_DMA_ChannelXTransferCountGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_DMA_ExistsChannelXDestinationPointer(DMA_MODULE_ID index)
bool DRV_IC0_BufferIsEmpty(void)
DRV_USART_CLIENT_STATUS DRV_USART_ClientStatus(DRV_HANDLE handle)
SPI_AUDIO_TRANSMIT_MODE audioTransmitMode
void PLIB_DMA_ChannelXReloadEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsFrameErrorStatus(SPI_MODULE_ID index)
static void DRV_TMR1_Close(void)
uint32_t DRV_TMR1_CounterFrequencyGet(void)
void PLIB_SPI_FramedCommunicationDisable(SPI_MODULE_ID index)
void PLIB_PORTS_ChangeNoticePullUpPerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_DMA_ExistsChannelXAbortIRQ(DMA_MODULE_ID index)
uintptr_t DRV_SPI_BUFFER_HANDLE
void DRV_TMR2_CounterValueSet(uint32_t value)
void PLIB_USART_RunInSleepModeEnable(USART_MODULE_ID index)
void PLIB_DMA_ChannelXINTSourceDisable(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
void PLIB_DMA_BusyActiveReset(DMA_MODULE_ID index)
void DRV_USART0_Close(void)
void SYS_DMA_TasksErrorISR(SYS_MODULE_OBJ object, DMA_CHANNEL activeChannel)
static void qqoutput(FILEPOINT char *s, int i)
bool PLIB_USART_ExistsModuleBusyStatus(USART_MODULE_ID index)
SPI_AUDIO_PROTOCOL audioProtocolMode
void PLIB_DMA_ChannelXBusyInActiveSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
DRV_SPI_CLOCK_MODE clockMode
bool PLIB_USART_RunInSleepModeIsEnabled(USART_MODULE_ID index)
SYS_STATUS DRV_USART_Status(SYS_MODULE_OBJ object)
bool PLIB_SPI_ExistsAudioCommunicationWidth(SPI_MODULE_ID index)
bool PLIB_PORTS_ExistsRemapInput(PORTS_MODULE_ID index)
void DRV_TMR2_StopInIdleDisable(void)
PORTS_DATA_MASK PLIB_PORTS_DirectionGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_PORTS_PinDirectionOutputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void DRV_TMR0_Initialize(void)
void PLIB_USART_ReceiverAddressDetectDisable(USART_MODULE_ID index)
bool PLIB_SPI_TransmitBufferIsFull(SPI_MODULE_ID index)
uintptr_t SYS_DMA_CHANNEL_HANDLE
DRV_USART_BAUD_SET_RESULT DRV_USART0_BaudSet(uint32_t baud)
#define DRV_IC_Close(handle)
static void DRV_TMR4_Close(void)
void SYS_DMA_ChannelSetupMatchAbortMode(SYS_DMA_CHANNEL_HANDLE handle, uint16_t pattern, DMA_PATTERN_LENGTH length, SYS_DMA_CHANNEL_IGNORE_MATCH ignore, uint8_t ignorePattern)
uint16_t PLIB_DMA_ChannelXSourcePointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
DRV_TMR_CLIENT_STATUS DRV_TMR4_ClientStatus(void)
void PLIB_DMA_ChannelXPrioritySelect(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_CHANNEL_PRIORITY channelPriority)
PORTS_DATA_TYPE SYS_PORTS_Read(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
bool PLIB_SPI_ExistsReceiverOverflow(SPI_MODULE_ID index)
void PLIB_PORTS_ChangeNoticeInIdlePerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
SYS_STATUS DRV_SPI_Status(SYS_MODULE_OBJ object)
static void qqoutput0(FILEPOINT char *s)
uint32_t DRV_TMR0_CounterValueGet(void)
void DRV_USART_AddressedBufferAddWrite(const DRV_HANDLE hClient, DRV_USART_BUFFER_HANDLE *bufferHandle, uint8_t address, void *source, size_t nWords)
DRV_USART_BAUD_SET_RESULT
bool PLIB_DMA_ExistsStopInIdle(DMA_MODULE_ID index)
void PLIB_SPI_SlaveSelectDisable(SPI_MODULE_ID index)
void PLIB_SPI_BaudRateClockSelect(SPI_MODULE_ID index, SPI_BAUD_RATE_CLOCK type)
void DRV_TMR1_StopInIdleDisable(void)
bool PLIB_USART_ReceiverIsIdle(USART_MODULE_ID index)
void APP_Initialize(void)
void PLIB_PORTS_ChannelSlewRateSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK channelMask, PORTS_PIN_SLEW_RATE slewRate)
void DRV_TMR2_PeriodValueSet(uint32_t value)
void PLIB_DMA_ChannelXDisable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_ReceiverAddressIsReceived(USART_MODULE_ID index)
bool PLIB_DMA_ExistsCRCData(DMA_MODULE_ID index)
uint32_t DRV_ADC_SamplesRead(uint8_t bufIndex)
void SYS_PORTS_PinDirectionSelect(PORTS_MODULE_ID index, SYS_PORTS_PIN_DIRECTION pinDir, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void DRV_TMR4_PeriodValueSet(uint32_t value)
INT_SOURCE rxInterruptSource
void DRV_TMR_Deinitialize(SYS_MODULE_OBJ object)
bool PLIB_SPI_ExistsReadDataSignStatus(SPI_MODULE_ID index)
bool PLIB_USART_ExistsReceiverDataAvailableStatus(USART_MODULE_ID index)
void SET_WL_SPS_IOffset(uint8_t mode)
void DRV_TMR3_PeriodValueSet(uint32_t value)
bool PLIB_USART_ExistsReceiverEnable(USART_MODULE_ID index)
bool PLIB_SPI_IsBusy(SPI_MODULE_ID index)
void PLIB_USART_ReceiverIdleStateLowEnable(USART_MODULE_ID index)
void PLIB_USART_RunInOverflowEnable(USART_MODULE_ID index)
uint32_t DRV_TMR2_CounterFrequencyGet(void)
void PLIB_USART_StopInIdleEnable(USART_MODULE_ID index)
void DRV_TMR_CounterValueSet(DRV_HANDLE handle, uint32_t counterPeriod)
SYS_MODULE_OBJ DRV_SPI_Initialize(const SYS_MODULE_INDEX index, const SYS_MODULE_INIT *const init)
DMA_CHANNEL PLIB_DMA_CRCChannelGet(DMA_MODULE_ID index)
bool DRV_TMR2_Start(void)
uint8_t PLIB_SPI_FIFOCountGet(SPI_MODULE_ID index, SPI_FIFO_TYPE type)
void PLIB_DMA_CRCDataWrite(DMA_MODULE_ID index, uint32_t DMACRCdata)
void PLIB_SPI_OutputDataPhaseSelect(SPI_MODULE_ID index, SPI_OUTPUT_DATA_PHASE phase)
INT_SOURCE errInterruptSource
void PLIB_USART_ReceiverIdleStateLowDisable(USART_MODULE_ID index)
void PLIB_SPI_Enable(SPI_MODULE_ID index)
void SYS_DMA_Suspend(void)
void PLIB_PORTS_PinDirectionInputSet(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
ldra_void_function qqqaccumreset[QQQnumfil]
int8_t PLIB_USART_ReceiverByteReceive(USART_MODULE_ID index)
bool PLIB_USART_ExistsStopInIdle(USART_MODULE_ID index)
TMR_PRESCALE DRV_TMR2_PrescalerGet(void)
void PLIB_SPI_FrameSyncPulseCounterSelect(SPI_MODULE_ID index, SPI_FRAME_SYNC_PULSE pulse)
bool DRV_IC_BufferIsEmpty(DRV_HANDLE handle)
bool PLIB_SPI_ExistsFIFOControl(SPI_MODULE_ID index)
bool DRV_USART_ReceiverBufferIsEmpty(const DRV_HANDLE handle)
void SYS_DMA_ChannelForceAbort(SYS_DMA_CHANNEL_HANDLE handle)
bool DRV_TMR_ClockSet(DRV_HANDLE handle, DRV_TMR_CLK_SOURCES clockSource, TMR_PRESCALE preScale)
void SYS_DEBUG_Message(const char *message)
uint16_t DRV_IC0_Capture16BitDataRead(void)
void DRV_TMR4_Initialize(void)
uint16_t PLIB_DMA_ChannelXCellProgressPointerGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel)
bool PLIB_SPI_ExistsAudioErrorControl(SPI_MODULE_ID index)
bool PLIB_SPI_ExistsFrameSyncPulseEdge(SPI_MODULE_ID index)
void PLIB_SPI_Disable(SPI_MODULE_ID index)
void DRV_PMP0_Initialize(void)
static void DRV_TMR2_Open(void)
void PLIB_PORTS_ChangeNoticePullDownPerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
DMA_PING_PONG_MODE PLIB_DMA_ChannelXPingPongModeGet(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_SPI_ExistsTransmitUnderRunStatus(SPI_MODULE_ID index)
void PLIB_PORTS_CnPinsDisable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
bool PLIB_PORTS_ExistsPortsOpenDrain(PORTS_MODULE_ID index)
void PLIB_DMA_ChannelXPatternIgnoreSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint8_t pattern)
void PLIB_DMA_ChannelXPatternIgnoreByteEnable(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool DRV_TMR1_Start(void)
bool PLIB_DMA_ExistsChannelXCellSize(DMA_MODULE_ID index)
void PLIB_DMA_SuspendEnable(DMA_MODULE_ID index)
SYS_STATUS DRV_USART0_Status(void)
bool PLIB_DMA_ExistsChannelXSourcePointer(DMA_MODULE_ID index)
bool PLIB_SPI_ExistsSlaveSelectControl(SPI_MODULE_ID index)
void DRV_TMR_Tasks(SYS_MODULE_OBJ object)
DRV_USART_LINE_CONTROL_SET_RESULT DRV_USART_LineControlSet(const DRV_HANDLE client, const DRV_USART_LINE_CONTROL lineControl)
bool PLIB_DMA_ExistsCRCWriteByteOrder(DMA_MODULE_ID index)
bool PLIB_PORTS_ExistsChangeNoticePerPortStatus(PORTS_MODULE_ID index)
void PLIB_PORTS_ChangeNoticeDisable(PORTS_MODULE_ID index)
void DRV_TMR3_StopInIdleEnable(void)
DRV_SPI_TASK_MODE taskMode
bool PLIB_DMA_ChannelXINTSourceFlagGet(DMA_MODULE_ID index, DMA_CHANNEL dmaChannel, DMA_INT_TYPE dmaINTSource)
void PLIB_DMA_ChannelXBusyActiveSet(DMA_MODULE_ID index, DMA_CHANNEL channel)
PORTS_DATA_MASK SYS_PORTS_DirectionGet(PORTS_MODULE_ID index, PORTS_CHANNEL channel)
void PLIB_DMA_ChannelXPeripheralAddressSet(DMA_MODULE_ID index, DMA_CHANNEL channel, uint16_t peripheraladdress)
SYS_MODULE_OBJ SYS_DMA_Initialize(const SYS_MODULE_INIT *const init)
void DRV_TMR_CounterClear(DRV_HANDLE handle)
void DRV_TMR0_CounterValueSet(uint32_t value)
uint32_t DRV_TMR_AlarmHasElapsed(DRV_HANDLE handle)
void DRV_USART_BufferAddWrite(const DRV_HANDLE handle, DRV_USART_BUFFER_HANDLE *bufferHandle, void *buffer, const size_t size)
bool PLIB_SPI_TransmitBufferIsEmpty(SPI_MODULE_ID index)
bool PLIB_DMA_CRCIsEnabled(DMA_MODULE_ID index)
void PLIB_DMA_CRCByteOrderSelect(DMA_MODULE_ID index, DMA_CRC_BYTE_ORDER byteOrder)
static void DRV_TMR3_Tasks(void)
bool DRV_TMR_AlarmRegister(DRV_HANDLE handle, uint32_t divider, bool isPeriodic, uintptr_t context, DRV_TMR_CALLBACK callBack)
void DRV_TMR4_CounterValueSet(uint32_t value)
static void DRV_TMR3_Close(void)
void SYS_DEBUG_ErrorLevelSet(SYS_ERROR_LEVEL level)
bool PLIB_SPI_Exists16bitBuffer(SPI_MODULE_ID index)
void SYS_DMA_ChannelEnable(SYS_DMA_CHANNEL_HANDLE handle)
static void qqqqinitialise(int ii)
void PLIB_PORTS_CnPinsPullUpDisable(PORTS_MODULE_ID index, PORTS_CN_PIN cnPins)
SYS_DMA_CHANNEL_CHAIN_PRIO
void PLIB_PORTS_PinChangeNoticePerPortDisable(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
void DRV_TMR1_PeriodValueSet(uint32_t value)
bool PLIB_SPI_ExistsAudioProtocolMode(SPI_MODULE_ID index)
void DRV_USART_BufferEventHandlerSet(const DRV_HANDLE handle, const DRV_USART_BUFFER_EVENT_HANDLER eventHandler, const uintptr_t context)
void PLIB_USART_TransmitterBreakSend(USART_MODULE_ID index)
void PLIB_PORTS_ChannelModeSelect(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_DATA_MASK modeMask, PORTS_PIN_MODE mode)
unsigned int DRV_USART0_TransmitBufferSizeGet(void)
void DRV_TMR1_StopInIdleEnable(void)
void PLIB_SPI_FIFOEnable(SPI_MODULE_ID index)
void PLIB_DMA_CRCWriteByteOrderMaintain(DMA_MODULE_ID index)
void PLIB_DMA_CRCChannelSelect(DMA_MODULE_ID index, DMA_CHANNEL channel)
bool PLIB_USART_ExistsEnable(USART_MODULE_ID index)
void DRV_SPI_Tasks(SYS_MODULE_OBJ object)
DRV_TMR_CLIENT_STATUS DRV_TMR0_ClientStatus(void)
TMR_PRESCALE DRV_TMR1_PrescalerGet(void)
void PLIB_USART_ReceiverAddressAutoDetectEnable(USART_MODULE_ID index, int8_t Mask)
SPI_FRAME_SYNC_PULSE frameSyncPulse
void DRV_USART0_TasksTransmit(void)
void PLIB_USART_Disable(USART_MODULE_ID index)
void DRV_TMR2_CounterClear(void)
int32_t DRV_SPI_ClientConfigure(DRV_HANDLE handle, const DRV_SPI_CLIENT_DATA *cfgData)
void PLIB_SPI_FrameSyncPulseWidthSelect(SPI_MODULE_ID index, SPI_FRAME_PULSE_WIDTH width)
uint8_t PLIB_DMA_CRCPolynomialLengthGet(DMA_MODULE_ID index)
bool PLIB_USART_ModuleIsBusy(USART_MODULE_ID index)
void PLIB_DMA_ChannelXAbortIRQSet(DMA_MODULE_ID index, DMA_CHANNEL channel, DMA_TRIGGER_SOURCE IRQ)
bool PLIB_DMA_ExistsChannelXSourceStartAddress(DMA_MODULE_ID index)
void PLIB_PORTS_PinToggle(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_USART_ExistsBaudRate(USART_MODULE_ID index)
static void qqbmsoutput(FILEPOINT char *s, unsigned int i)
uint8_t PLIB_DMA_ChannelBitsGet(DMA_MODULE_ID index)
void PLIB_USART_LineControlModeSelect(USART_MODULE_ID index, USART_LINECONTROL_MODE dataFlowConfig)
size_t DRV_USART_Read(const DRV_HANDLE handle, void *buffer, const size_t numbytes)
bool PLIB_SPI_ExistsAudioProtocolControl(SPI_MODULE_ID index)
static int wl_sps_50zscanf(char *qqscan_str)
void SYS_DMA_ChannelCRCSet(SYS_DMA_CHANNEL_HANDLE handle, SYS_DMA_CHANNEL_OPERATION_MODE_CRC crc)
bool PLIB_DMA_ExistsChannelXDisabled(DMA_MODULE_ID index)
bool PLIB_PORTS_ChangeNoticePerPortHasOccurred(PORTS_MODULE_ID index, PORTS_CHANNEL channel, PORTS_BIT_POS bitPos)
bool PLIB_USART_ExistsReceiver(USART_MODULE_ID index)
uint32_t DRV_TMR1_CounterValueGet(void)
static void DRV_TMR2_Tasks(void)
uint32_t SYS_DMA_ChannelCRCGet(void)
DMA_CHANNEL_PRIORITY PLIB_DMA_ChannelPriorityGet(DMA_MODULE_ID index)
bool PLIB_DMA_ExistsStartTransfer(DMA_MODULE_ID index)
bool PLIB_SPI_ExistsReceiveFIFOStatus(SPI_MODULE_ID index)
void qqpopulate_array_fcn_ptrQQ(int x, ldra_void_function y, ldra_void_function z)
PORTS_DATA_TYPE PLIB_PORTS_ReadLatched(PORTS_MODULE_ID index, PORTS_CHANNEL channel)